Accelerating program execution using hybrid control flow and dataflow architectures

Milutinović, Veljko; Trifunović, Nemanja; Korolija, Nenad; Popovic, Jovan; Bojic, Dragan

doi:10.1109/telfor.2017.8249476

Cited by 5 publications

(3 citation statements)

References 7 publications

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“…The work described in the open literature shows that algorithms can benefit from performance improvements using hybrid architectures [27][28]. However, the acceleration requires special job scheduling algorithms that combine both control-flow and dataflow jobs [29], as the scheduling parameters differ substantially from those of any of the two types of architectures.…”

Section: Methodsmentioning

confidence: 99%

Merging control-flow and dataflow architectures on a single chip

Korolija,

Štrbac-Savić

2024

J Comp Foren Sci

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Computing power rises predominantly by increasing the number of cores in modern processors and the number of processors in cluster and cloud architectures. Along with increasing processing power, high-performance computing requirements also rise. The majority of the computing infrastructure includes control-flow processors that are based on the von Neumann paradigm. On the contrary, the principle of dataflow architectures is based on the data flowing through the already configured hardware. Recent research has proposed hybrid architectures, where both control-flow and dataflow hardware would exist on the same chip die. This article proposes a new hybrid control-flow and dataflow architecture where the control-flow hardware resembles modern graphical cards with thousands of cores and each GPU core has a reasonable amount of data-flow hardware. In this way, the advantages of dataflow architecture are exploited, including faster processing of high-performance computing algorithms and lower power consumption, while the conventional problem of communicating between control-flow and dataflow architectures is minimized. The proposed architecture is tested by analyzing the conjugate gradient method executed on both control-flow and dataflow hardware. The execution of the algorithm is divided onto GPU cores, and the execution of repeated instructions on each GPU core is delegated to the assigned dataflow hardware. The results indicate that it is possible to accelerate the execution of algorithms using the proposed architecture.

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Section: Methodsmentioning

confidence: 99%

Merging control-flow and dataflow architectures on a single chip

Korolija,

Štrbac-Savić

2024

J Comp Foren Sci

Self Cite

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“…Researchers have developed a prototype of a hybrid processor consisting of both control-flow and dataflow hardware [13][14][15]. Both multicore processor and so called manycore processor are included as a control-flow hardware.…”

Section: Hybrid Architecturesmentioning

confidence: 99%

Fine Grain Algorithm Parallelization on a Hybrid Control-flow and Dataflow Processor

Korolija

Furht

Milutinović

2023

Preprint

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The execution time of a high performance computing algorithm depends on multiple factors: the algorithm scalability, the chosen hardware, the communication speed between processing elements, etc. This work is based on a hybrid processor consisting of both the control-flow and dataflow hardware, where the control-flow hardware includes manycore architecture. The algorithm decomposition into portions suitable for different architectures is presented. The results are presented by decomposing the Lattice-Boltzmann method implemented for both control-flow and dataflow hardware. The total acceleration factor of the decomposed Lattice-Boltzmann method comparing to the execution time using the control-flow and the dataflow hardware is obtained by the analysis based on the speed of the communication between both hardware equal to the speed of shared cache memories. Results indicate the advantage of using the proposed hybrid architecture and the capability of accelerating considerably even the suitable for dataflow architectures. The analysis of the problem size needed to justify the utilization of control-flow hardware is also presented. The main benefit is in accelerating algorithms for which only some algorithm portions are suitable for the dataflow hardware.

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“…Programming dataflow architectures is considered to be reasonably harder compared to programming control-flow architectures [3]. Despite that, there are a lot of algorithms implemented for dataflow architectures [4], as well as methods to automate the translation of control-flow software into the dataflow [5,6]. Placing both controlflow and dataflow components with shared memory at the same chip die requires special techniques [7][8][9][10], while it reduces the lifespan of a chip to the minimum lifespan of its components [11].…”

Section: Advanced Technologies and Applications Session Invited Papermentioning

confidence: 99%

Scratchpad Memory Unit in Hybrid Control-flow and Dataflow Architectures

Korolija¹,

Štrbac-Savić²,

Đorđević³

2023

Proceedings of the International Scientific Conference - Sinteza 2023

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Dataflow architectures offer superior performance compared to control-flow architectures under certain conditions. This paper focuses on memory organization of a hybrid control-flow and dataflow architecture which guaranties that memory allocation can be accomplished in a predictable time. Mapping logical addresses into physical ones and accessing local memory in constant time is achieved using special address translation hardware. The memory organization is based on Buddy-system. It allows allocating arbitrary amounts of memory and prefetching data while it is being accessed by control-flow and dataflow hardware.

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Accelerating program execution using hybrid control flow and dataflow architectures

Cited by 5 publications

References 7 publications

Merging control-flow and dataflow architectures on a single chip

Merging control-flow and dataflow architectures on a single chip

Fine Grain Algorithm Parallelization on a Hybrid Control-flow and Dataflow Processor

Scratchpad Memory Unit in Hybrid Control-flow and Dataflow Architectures

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