Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction

Bombieri, Nicola; Fummi, Franco; Guarnieri, Valerio

doi:10.1109/ets.2011.58

Cited by 10 publications

(3 citation statements)

References 16 publications

(17 reference statements)

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“…Bombieri et al [25] in 2011 utilize Transaction-Level Modeling vastly used for functional verification at the system level in order to optimize the fault simulation. The proposed approach claims the automatic extraction of the TLM models from the RTL description.…”

Section: Acceleration Via Complexity Abstractionmentioning

confidence: 99%

Enabling ISO 26262 Compliance with Accelerated Diagnostic Coverage Assessment

2020

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Modern vehicles are integrating a growing number of electronics to provide a safer experience for the driver. Therefore, safety is a non-negotiable requirement that must be considered through the vehicle development process. The ISO 26262 standard provides guidance to ensure that such requirements are implemented. Fault injection is highly recommended for the functional verification of safety mechanisms or to evaluate their diagnostic coverage capability. An exhaustive analysis is not required, but evidence of best effort through the diagnostic coverage assessment needs to be provided when performing quantitative evaluation of hardware architectural metrics. These metrics support that the automotive safety integrity level—ranging from A (lowest) to D (strictest) levels—was obeyed. In this context, this paper proposed a verification solution in order to build an approach that can accelerate the diagnostic coverage assessment via fault injection in the semiconductor level (i.e., hardware description language). The proposed solution does not require any modification of the design model to enable acceleration. Small parts of the OpenRISC architecture (namely a carry adder, the Tick Timer peripheral, and the exception block) were used to illustrate the methodology.

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Section: Acceleration Via Complexity Abstractionmentioning

confidence: 99%

Enabling ISO 26262 Compliance with Accelerated Diagnostic Coverage Assessment

2020

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“…To achieve this, several approaches have been recently investigated, such as mutation schema [21], model abstraction [28], hardware acceleration [29], software emulation [30], and directed test generation [20,22].…”

Section: Testbench Qualificationmentioning

confidence: 99%

Safety Evaluation of Automotive Electronics Using Virtual Prototypes

Oetjens

Bannow

Becker

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults.Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on today's industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.

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“…There has been a massive amount of research trying to improve the fault simulation time on single-core [6], [7] and multi-core systems [8], [9]. Beside the ideas to improve the simulation of circuit, e.g., event-driven and multi-thread simulation techniques, there has been several ideas that exploit the independent effect of different faults on the circuit to increase the parallelization of fault simulation, e.g., parallel fault simulation [8], [9] and concurrent fault simulation [10].…”

Section: Introductionmentioning

confidence: 99%

Thread-level Parallelism in Fault Simulation of Deep Neural Networks on Multi-Processor Systems

Karami

Haghbayan

Ebrahimi

et al. 2022

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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High-performance fault simulation is one of the essential and preliminary tasks in the process of online and offline testing of machine learning (ML) hardware. Deep neural networks (DNN), as one of the essential parts of ML programs, are widely used in many critical and non-critical applications in Systems-on-Chip and ASIC designs. Through fault simulation for DNNs, by increasing the number of neurons, the fault simulation time increases exponentially. However, the software architecture of neural networks and the lack of dependency between neurons in each inference layer provide significant opportunity for parallelism of the fault simulation time in a multi-processor platform. In this paper, a multi-thread technique for hierarchical fault simulation of neural network is proposed, targeting both permanent and transient faults. During the process of fault simulation the neurons for each inference layer will be distributed among the executing threads. Since in the process of hierarchical fault simulation, the faulty neuron demands proportionally enormous computation comparing to behavioural model of non-faulty neurons, the faulty neuron will be assigned to one thread while the rest of the neurons will be divided among the remaining threads. Experimental results confirm the time efficiency of the proposed fault simulation technique on multiprocessor architectures.

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Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction

Cited by 10 publications

References 16 publications

Enabling ISO 26262 Compliance with Accelerated Diagnostic Coverage Assessment

Enabling ISO 26262 Compliance with Accelerated Diagnostic Coverage Assessment

Safety Evaluation of Automotive Electronics Using Virtual Prototypes

Thread-level Parallelism in Fault Simulation of Deep Neural Networks on Multi-Processor Systems

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