Accelerating Spike-by-Spike Neural Networks on FPGA With Hybrid Custom Floating-Point and Logarithmic Dot-Product Approximation

Nevarez, Yarib; Rotermund, David; Pawelzik, Klaus; García-Ortiz, Alberto

doi:10.1109/access.2021.3085216

Cited by 6 publications

(2 citation statements)

References 40 publications

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“…IaF networks are biologically more realistic than SbS networks, but require orders of magnitude more computational power than SbS [10]. Furthermore, it is possible to construct very efficient hardware accelerators for SbS [11]. A Github with our PyTorch SbS and NNMF framework can be found at https://github.com/davrot/pytorch-sbs…”

Section: Discussionmentioning

confidence: 99%

Competitive performance and superior noise robustness of a non-negative deep convolutional spiking network

Rotermund

García-Ortiz

Pawelzik

2023

Preprint

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Networks of spiking neurons promise to combine energy efficiency with high performance. However, spiking models that match the performance of current state-of-the-art networks while requiring moderate computational resources are still lacking. Here we present an alternative framework to deep convolutional networks (CNNs), the "Spike by Spike" network (SbS), together with an efficient backpropagation algorithm. SbS implements networks based on non-negative matrix factorisation (NNMF), but uses discrete events as signals instead of real values. On clean data, the performance of CNNs is matched by both NNMF-based networks and SbS. SbS are found to be most robust when the data is corrupted by noise, specially when this noise was not seen before.

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Section: Discussionmentioning

confidence: 99%

Competitive performance and superior noise robustness of a non-negative deep convolutional spiking network

Rotermund

García-Ortiz

Pawelzik

2023

Preprint

Self Cite

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“…We implement the floating-point computation adopting the dot-product with hybrid custom floating-point [29]. The hardware dot-product is illustrated in Fig.…”

Section: ) Dot-product With Hybrid Floating-pointmentioning

confidence: 99%

CNN Sensor Analytics With Hybrid-Float6 Quantization on Low-Power Embedded FPGAs

et al. 2023

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The use of artificial intelligence (AI) in sensor analytics is entering a new era based on the use of ubiquitous embedded connected devices. This transformation requires the adoption of design techniques that reconcile accurate results with sustainable system architectures. As such, improving the efficiency of AI hardware engines as well as backward compatibility must be considered. In this paper, we present the Hybrid-Float6 (HF6) quantization and its dedicated hardware design. We propose an optimized multiply-accumulate (MAC) hardware by reducing the mantissa multiplication to a multiplexor-adder operation. We exploit the intrinsic error tolerance of neural networks to further reduce the hardware design with approximation. To preserve model accuracy, we present a quantization-aware training (QAT) method, which in some cases improves accuracy. We demonstrate this concept in 2D convolution layers. We present a lightweight tensor processor (TP) implementing a pipelined vector dot-product. For compatibility and portability, the 6-bit floating-point (FP) is wrapped in the standard FP format, which is automatically extracted by the proposed hardware. The hardware/software architecture is compatible with TensorFlow (TF) Lite. We evaluate the applicability of our approach with a CNN-regression model for anomaly localization in a structural health monitoring (SHM) application based on acoustic emission (AE). The embedded hardware/software framework is demonstrated on XC7Z007S as the smallest Zynq-7000 SoC. The proposed implementation achieves a peak power efficiency and run-time acceleration of 5.7 GFLOPS/s/W and 48.3×, respectively.

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Low power adders using asynchronous pipelined modified low voltage MCML for signal processing and communication applications

KalavathiDevi,

Renuka Devi,

Umadevi

et al. 2024

Analog Integr Circ Sig Process

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Accelerating Spike-by-Spike Neural Networks on FPGA With Hybrid Custom Floating-Point and Logarithmic Dot-Product Approximation

Cited by 6 publications

References 40 publications

Competitive performance and superior noise robustness of a non-negative deep convolutional spiking network

Competitive performance and superior noise robustness of a non-negative deep convolutional spiking network

CNN Sensor Analytics With Hybrid-Float6 Quantization on Low-Power Embedded FPGAs

Low power adders using asynchronous pipelined modified low voltage MCML for signal processing and communication applications

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