Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays

Smékal, David; Frolka, Jakub; Hajný, Jan

doi:10.1016/j.ifacol.2016.12.075

Cited by 12 publications

(5 citation statements)

References 8 publications

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“…In addition, on Xilinx Virtex-5 FPGA AES encryptor achieved 119.5 Gbps throughput [11] for 100G Ethernet, and 102 Gbps throughout was reached on Xilinx Virtex-7 [12]. Other FPGA based encryptors in the literature [13][14][15][16][17][18][19] have achieved encryption throughputs between 0.4-86 Gbps. Probably one of the most important encryptors for optical networks was reported in [12], where 3 different algorithms were accommodated on the FPGA firmware and AES, Galois/Counter Mode (GCM) and Internet Protocol Security (IPSec) have been provided up to network throughput of 200 Gbps with theoretical AES throughput of 48.38 Gbps.…”

Section: State-of-the-artmentioning

confidence: 98%

100 Gb/s dynamically programmable SDN-enabled hardware encryptor for optical networks

Arabul

Tessinari

Alia

et al. 2021

J. Opt. Commun. Netw.

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We have successfully demonstrated an on-demand programmable hardware encryptor for optical networks enabled by the software-defined network (SDN) and tested its application in a quantum key distribution (QKD) use case. We believe our proposed encryptor is unique in the way that it combines on-demand programmable encryption algorithms with a 100G Ethernet network interface to provide a high-transmission capacity with flexible security. We have successfully formed an on-demand encryption library consisting of AES-256, AES-192, AES-128, Camellia-256, XOR, and no-encryption configurations. Our system has shown a network throughput of 91.3 Gb/s for AES variations and 90.2 Gb/s for Camellia-256, while theoretical encryption throughputs were 160 Gb/s. In addition, the goodputs of all the encryption schemes were measured as at least 90.4 Gb/s. For a faster reconfiguration of the field-programmable gate array (FPGA), partial reconfiguration technology has been used, and reconfiguration times of 2.6 s for encryption and 2 s for decryption have been achieved. The FPGA configuration rate was 3.35 MB/s. When our proposed design was tested in a QKD use case with 256-bit keys, the highest achieved key consumption rate was 27 keys/s, which corresponded to the minimum granularity of 474 MB per key. Thus, with a 256-bit key, up to a 6912 b/s key consumption rate was achieved. In addition, the encryptor’s end-to-end network latency has been tested using 300k standard Internet Control Message Protocol (ICMP) pings. For all encryption schemes, the latency was measured as 0.093 m s ± 0.028 m s on average, but the encryption/decryption processes did not have a meaningful latency impact with microsecond precision.

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Section: State-of-the-artmentioning

confidence: 98%

100 Gb/s dynamically programmable SDN-enabled hardware encryptor for optical networks

Arabul

Tessinari

Alia

et al. 2021

J. Opt. Commun. Netw.

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“…Keamanan memiliki peran penting dalam memfasilitasi adopsi teknologi dan aplikasi yang lebih luas dalam berbagai aspek kehidupan [1]. Pada saat yang sama, ilmu kriptografi saat ini sangat berfokus pada dua hal utama, yaitu keamanan data dan kecepatan dalam mentransmisikan informasi [2]. Pada saat yang sama, ilmu kriptografi saat ini sangat berfokus pada dua hal utama, yaitu keamanan data dan kecepatan dalam mentransmisikan informasi [3].…”

Section: Pendahuluanunclassified

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Gunawan,

Yuda,

Bintari

et al. 2024

tektrika

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Penelitian ini bertujuan untuk menganalisis kinerja kriptografi RSA pada sistem operasi Windows 11 dengan implementasi menggunakan Python dan aplikasi NZXT CAM. Metode penelitian yang digunakan adalah pendekatan kuantitatif, dengan spesifikasi prosesor 2.80GHz, 8 inti, dan RAM 16 GB. Data dikumpulkan melalui aplikasi benchmark NZXT CAM, yang mengukur penggunaan CPU dan memori selama proses generasi kunci, enkripsi, dan dekripsi dengan algoritma RSA. Hasil penelitian menunjukkan korelasi langsung antara panjang kunci RSA dan beban CPU serta waktu yang dibutuhkan untuk proses kriptografi. Ditemukan bahwa kunci RSA yang lebih panjang mengakibatkan peningkatan penggunaan sumber daya komputasi. Misalnya, kunci RSA 1024 bit menggunakan rata-rata 10% beban CPU dan 53,1 MB memori, sedangkan kunci 2048 bit meningkat menjadi 11,6% beban CPU dan 53,4 MB memori. Kunci 4096 bit memerlukan 10,6% beban CPU dengan penggunaan memori yang serupa, namun waktu proses meningkat dari 2,5 detik menjadi 27,7 detik. Kesimpulan dari penelitian ini memberikan wawasan penting bagi pengembangan aplikasi keamanan di Windows 11, khususnya dalam keseimbangan antara panjang kunci dan penggunaan sumber daya. Disarankan penelitian selanjutnya untuk mengevaluasi kinerja RSA pada berbagai konfigurasi perangkat keras.

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“…In general, the strength of a cryptographic product can be increased by increasing the number of cycles it takes to process the data. The AES standard states that the number of cycles is determined by the length of the numeric key [20,21], as shown in Table I.…”

Section: A Advance Encryption Standard (Aes)mentioning

confidence: 99%

International Journal of Electronics and Telecommunications

Pattanavichai

2022

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Nowadays, information security management systems are important parts of managing a system for better handling of the information security. In scenarios and situations where safety management is done by managing protection of malwares, it is important to manage security issues properly. Cryptography is an approach which makes possible for a recipient to encrypt and decrypt the information. A combination of two different strategies for encryption and decryption in the text encoding will be transformed into the used all content. The encryption and decryption key of the content decryption key is used. There are different types of information. A number, such as finding two large prime numbers with that product. The number, the size of the RSA key is large enough to make, it's hard to pinpoint these numbers. The key, known as the RSA public key, is the most prominent open encryption. Calculations were used for information exchange. In this paper, we created a program for simulation and testing of apply cryptography of Advance Encryption Standard (AES) algorithm with Rivest-Shamir-Adleman (RSA) algorithm for better performance. In this study, this program is an application of a new algorithm to be the AES&RSA principle of using a public key instead of a private key for cryptography, and the testing of encryption and decryption for the AES&RSA algorithm resulted in time is no different on the AES algorithm and more secure encryption and decryption. The results indicated that the time needed for encoding and decoding of AES&RSA algorithm has been reduced (i.e., efficiency has been improved).

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Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays

Cited by 12 publications

References 8 publications

100 Gb/s dynamically programmable SDN-enabled hardware encryptor for optical networks

100 Gb/s dynamically programmable SDN-enabled hardware encryptor for optical networks

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International Journal of Electronics and Telecommunications

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