Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications

Geurts, Werner

doi:10.1007/978-1-4419-8720-4

Cited by 28 publications

(30 citation statements)

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“…Whether a truly optimal algorithmic flow exists is still an open-research question. We believe that our solution can still be improved by the following extensions: 1) combining our approach with pattern-matching techniques [16], [27]- [29] in order to improve the utilization of the custom instructions we generate and 2) integrating our approach with datapathmerging techniques [32]- [34] in order to exploit partial resource sharing across custom instructions for area-efficient synthesis.…”

Section: Discussionmentioning

confidence: 99%

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CHIPS: Custom Hardware Instruction Processor Synthesis

Atasu

Özturan

Dündar

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper describes an integer-linear-programming (ILP)-based system called Custom Hardware Instruction Processor Synthesis (CHIPS) that identifies custom instructions for critical code segments, given the available data bandwidth and transfer latencies between custom logic and a baseline processor with architecturally visible state registers. Our approach enables designers to optionally constrain the number of input and output operands for custom instructions. We describe a design flow to identify promising area, performance, and code-size tradeoffs. We study the effect of input/output constraints, register-file ports, and compiler transformations such as if-conversion. Our experiments show that, in most cases, the solutions with the highest performance are identified when the input/output constraints are removed. However, input/output constraints help our algorithms identify frequently used code segments, reducing the overall area overhead. Results for 11 benchmarks covering cryptography and multimedia are shown, with speed-ups between 1.7 and 6.6 times, code-size reductions between 6% and 72%, and area costs ranging between 12 and 256 adders for maximum speed-up. Our ILP-based approach scales well: benchmarks with basic blocks consisting of more than 1000 instructions can be optimally solved, most of the time within a few seconds.Index Terms-Application-specific instruction-set processors (ASIPs), custom instructions, customizable processors, extensible processors, integer linear programming (ILP), optimization algorithms.

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Section: Discussionmentioning

confidence: 99%

“…Dimond et al [31] introduced a customizable soft processor with multithreading support. Techniques that can exploit structural similarities across custom instructions for area-efficient synthesis are described in [32]- [34].…”

Section: Background and Related Workmentioning

confidence: 99%

CHIPS: Custom Hardware Instruction Processor Synthesis

Atasu

Özturan

Dündar

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Constraint (7) ensures that each incoming edge to a commutative operation connects to one input port; constraint (8) ensures that each input port has one incoming edge connecting to it. To simplify notation, let…”

Section: Optimal Integer Linear Program (Ilp) Formulationmentioning

confidence: 99%

“…Geurts [7] presented a DPM heuristic based on maximum bipartite matching; van der Werf et al [16] built a similar heuristic, but used simulated annealing instead. These approaches estimate an upper bound on the cost of muxes, but do not model the cost exactly.…”

Section: Related Workmentioning

confidence: 99%

A high-level synthesis flow for custom instruction set extensions for application-specific processors

Pothineni¹,

Brisk

Ienne

et al. 2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-Custom instruction set extensions (ISEs) are added to an extensible base processor to provide application-specific functionality at a low cost. As only one ISE executes at a time, resources can be shared. This paper presents a new high-level synthesis flow targeting ISEs. We emphasize a new technique for resource allocation, binding, and port assignment during synthesis. Our method is derived from prior work on datapath merging, and increases area reduction by accounting for the cost of multiplexors that must be inserted into the resulting datapath to achieve multi-operational functionality.

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“…the granularity at which code is considered: fine-grained and coarse-grained. The first one works at the operation level and implements small clusters of operations in HW [7,10,12,13,14,43,59,44]; the second one operates at the loop or procedure level and identifies critical loops or procedures in the application, and displaces them from SW to HW as a whole [16,17,18,19,20,21]. The main differences are in terms of speedups and flexibility: although a coarse-grained approach could produce a large speedup, its flexibility is limited, given that this approach is often performed on a per application basis and it is difficult that other applications have the same loop or procedure as critical part.…”

Section: Introduction To the Problemmentioning

confidence: 99%

The Instruction-Set Extension Problem: A Survey

Galuzzi

Bertels

Lecture Notes in Computer Science

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Abstract.Over the last years, we have witnessed the increased use of Application-Specific Instruction-Set Processors (ASIPs). These ASIPs are processors that have a customizable instruction-set, which can be tuned towards specific requirements. The identification, definition and implementation of those operations that provide the largest performance improvement and that should be hardwired, extending in this way the Instruction-Set, constitutes a major challenge. The purpose of this paper is to investigate and study the issues regarding the customization of an Instruction-Set in function of the specific requirements of an application. Additionally, the paper provides an overview of all relevant aspects of the problem and compensates the lack of a general view of the problem in the existing literature.

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Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications

Cited by 28 publications

References 0 publications

CHIPS: Custom Hardware Instruction Processor Synthesis

CHIPS: Custom Hardware Instruction Processor Synthesis

A high-level synthesis flow for custom instruction set extensions for application-specific processors

The Instruction-Set Extension Problem: A Survey

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