Accelerators for biologically-inspired attention and recognition

Abstract

Video and image content has begun to play a growing role in many applications, ranging from video games to autonomous self-driving vehicles. In this paper, we present accelerators for gist-based scene recognition, saliency-based attention, and HMAX-based object recognition that have multiple uses and are based on the current understanding of the vision systems found in the visual cortex of the mammalian brain. By integrating them into a two-level hierarchical system, we improve recognition accuracy and reduce computational time.Results of our accelerator prototype on a multi-FPGA system show real-time performance and high recognition accuracy with large speedups over existing CPU, GPU and FPGA implementations.

A Bottom-up Approach for Visual Object Recognition on FPGA based Embedded Multiprocessor Architecture

“…For example, in [16], the authors have suggested a real time implementation of their proposed saliency based algorithm on a highly parallel Single Instruction Multiple Data (SIMD) architecture called ProtoEye, which consists of a 2D array of mixed analogdigital processing elements (PE). Recent efforts were presented in [17] [18], which propose a parallel implementation of this model with multi-GPU and multi-FPGA system reaching real time performance and good recognition accuracy.…”

“…The Table III represents the speedups in execution time gained by our pipeline architecture and two existing HMAX accelerators implementations for 256 × 256 grayscale images [10] [18]. The initial design of the HMAX accelerator [10] takes about 21.81ms per image with a frame rate of 45.85 fps, whereas the second design [18] takes about 11.04ms per image with a frame rate of 90.57f ps. Our multi-processor architecture gave an overall speedups of 3.14X and 1.52X over the initial design and the second design, although it is mapped to a single FPGA only.…”

Towards General-Purpose Neural Network Computing

“…Much work has already been completed on the design of dedicated hardware for acceleration of MLPs [18]- [23] or other types of NNs, be they Convolutional Neural Networks [5]- [9], Deep Belief Networks [10]- [12], Hierarchical Model and X [13], or more biologically accurate models [14]- [17]. We, however, propose what we believe is the first instance of an NN accelerator architecture that supports the simultaneous execution of multiple NNs.…”

“…Such an interface allows NN hardware diversity to expand while, at the same time, encouraging a diverse set of software use cases to be explored. From a hardware perspective, one would like to see the continued exploration of the full spectrum of NN accelerator technologies from dedicated NN digital logic units [5]- [13], [18]- [23] to biologically inspired analog/sub-threshold implementations [14]- [17]. Similarly, from a software perspective, one wants to encourage both explicit and implicit usage models to grow.…”