Access Regulation to Hot-Modules in Wormhole NoCs

Walter, Isask'har; Cidon, Israel; Ginosar, Ran; Kolodny, Avinoam

doi:10.1109/nocs.2007.8

Cited by 27 publications

(11 citation statements)

References 22 publications

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“…It remains to be seen if PQS can be extended to provide QoS support. Source throttling [52,19] has been proposed to prevent buffer congestion but these have been proposed on top of conventional, buffered flow control or bufferless networks. Grot et al [13] also proposed a hybrid flow control in their kilo-NoC but their hybrid flow control combined elastic-buffered flow control with minimal VC flow control.…”

Section: Related Workmentioning

confidence: 99%

Transportation-network-inspired network-on-chip

Kim

Maeng

et al. 2014

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

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A cost-efficient network-on-chip is needed in a scalable many-core systems. Recent multicore processors have leveraged a ring topology and hierarchical ring can increase scalability but presents different challenges, including higher hop count and global ring bottleneck. In this work, we describe a hierarchical ring topology that we refer to as a transportationnetwork-inspired network-on-chip (tNoC) that leverages principles from transportation network systems. In particular, we propose a novel hybrid flow control for hierarchical ring topology to scale the topology efficiently. The flow control is hybrid in that the channels are allocated on flit granularity while the buffers are allocated on packet granularity. The hybrid flow control enables a simplified router microarchitecture (to minimize per-hop latency) as router input buffers are minimized and buffers are pushed to the edges, either at the output ports or at the hub routers that interconnect the local rings to the global ring -while still supporting virtual channels to avoid protocol deadlock. We also describe a packet-quota-system (PQS) and a separate credit network that provide congestion management, support prioritized arbitration in the network, and provide support for multiflit packets. A detailed evaluation of a 64-core CMP shows that the tNoC improves performance by up to 21% compared with a baseline, buffered hierarchical ring topology while reducing NoC energy by 51%.

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Section: Related Workmentioning

confidence: 99%

Transportation-network-inspired network-on-chip

Kim

Maeng

et al. 2014

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

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“…To reduce the traffic to DRAM the authors propose in [24] to have a processor base DRAM controller capable to process complex requests and return only the results. A credit based flow control method is used in [25] to prevent the DRAM traffic from waiting into the network and interfering with non DRAM traffic. In [26] the authors propose to give higher priority to transactions waiting in the DRAM queue that have to be sent back to cores in areas of the NoC which are less congested.…”

Section: Related Workmentioning

confidence: 99%

A distributed interleaving scheme for efficient access to WideIO DRAM memory

Seiculescu

Benini

Micheli

2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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Achieving the main memory (DRAM) required bandwidth at acceptable power levels for current and future applications is a major challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM memories promise to provide a significant boost in bandwidth at low power levels by exploiting multiple channels and wide data interfaces. In this paper, we address the problem of efficiently exploiting the multiple channels provided by standard (JEDEC's WIDE-IO) 3D-stacked memories, to extract maximal effective bandwidth and minimize latency for main memory access. We propose a new distributed interleaved access method that leverages the on-chip interconnect to simplify the design and implementation of the DRAM controller, without impacting performance compared to traditional centralized implementations. We perform experiments on realistic workload for a mobile communication and multimedia platform and show that our proposed distributed interleaving memory access method improves the overall throughput while minimally impacting the performance of latency sensitive communication flows.

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“…A credit based flow control method is used in [20] to prevent the DRAM traffic from waiting into the network and interfering with non DRAM traffic. In this work we propose the use of a separated DRAM network to prevent non DRAM traffic to be blocked by DRAM traffic.…”

Section: Related Workmentioning

confidence: 99%

“…However end-to-end flow control requires the use of a specialized mechanism to notify the cores of the state of the DRAM. For example a separate network or high priority virtual channel [20] can be used. This not only increases the design complexity, but also the buffering requirements needed to drain the messages that are already in the network.…”

Section: Introductionmentioning

confidence: 99%