Accounting for Cache Related Pre-emption Delays in Hierarchical Scheduling

Lunniss, Will; Altmeyer, Sebastian; Lipari, Giuseppe; Davis, Robert I.

doi:10.1145/2659787.2659797

Cited by 11 publications

(4 citation statements)

References 20 publications

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“…These approaches were later superseded by multi-set based methods (ECB-Union Multi-set and UCB-Union Multi-set) which dominate them [3]. These methods have been adapted to EDF scheduling [17], [20] and to hierarchical scheduling with local fixed priority [18] and EDF [19] schedulers. They have also been integrated into analysis for multi-core systems [1].…”

Section: A Related Workmentioning

confidence: 99%

Integrated Analysis of Cache Related Preemption Delays and Cache Persistence Reload Overheads

Rashid

Nelissen²,

Altmeyer

et al. 2017

2017 IEEE Real-Time Systems Symposium (RTSS)

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Schedulability analysis for tasks running on micro-processors with cache memory is incomplete without a treatment of Cache Related Preemption Delays (CRPD) and CachePersistence Reload Overheads (CPRO). State-of-theart analysescompute CRPD and CPRO independently, which might result incounting the same overhead more than once.In this paper, we analyze the pessimism associated with theindependent calculation of CRPD and CPRO in comparison toan integrated approach. We answer two main questions: (1) Isit beneï¬•cial to integrate the calculation of CRPD and CPRO?(2) When and to what extent can we gain in terms of schedu-lability by integrating the calculation of CRPD and CPRO? Toachieve this, we (i) identify situations where considering CRPDand CPRO separately might result in overestimating the totalmemory overhead suffered by tasks, (ii) derive new analyses thatintegrate the calculation of CRPD and CPRO; and (iii) perform athorough experimental evaluation using benchmarks to comparethe performance of the integrated analysis against the separatecalculation of CRPD and CPRO. Abstract-Schedulability analysis for tasks running on microprocessors with cache memory is incomplete without a treatment of Cache Related Preemption Delays (CRPD) and Cache Persistence Reload Overheads (CPRO). State-of-the-art analyses compute CRPD and CPRO independently, which might result in counting the same overhead more than once.In this paper, we analyze the pessimism associated with the independent calculation of CRPD and CPRO in comparison to an integrated approach. We answer two main questions: (1) Is it beneficial to integrate the calculation of CRPD and CPRO? (2) When and to what extent can we gain in terms of schedulability by integrating the calculation of CRPD and CPRO? To achieve this, we (i) identify situations where considering CRPD and CPRO separately might result in overestimating the total memory overhead suffered by tasks, (ii) derive new analyses that integrate the calculation of CRPD and CPRO; and (iii) perform a thorough experimental evaluation using benchmarks to compare the performance of the integrated analysis against the separate calculation of CRPD and CPRO.

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Section: A Related Workmentioning

confidence: 99%

Integrated Analysis of Cache Related Preemption Delays and Cache Persistence Reload Overheads

Rashid

Nelissen²,

Altmeyer

et al. 2017

2017 IEEE Real-Time Systems Symposium (RTSS)

Self Cite

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“…These approaches were later superseded by multiset based methods (ECB-Union Multiset and UCB-Union Multiset) which dominate them ). These methods have been adapted by Lunniss et al (2013Lunniss et al ( , 2014a to EDF scheduling and to hierarchical scheduling with local fixed-priority (Lunniss et al 2014b) and EDF ) schedulers. They have also been integrated into a response time analysis framework for multicore systems (Altmeyer et al 2015).…”

Section: Accounting For Overheads In Schedulability Analysismentioning

confidence: 99%

Response-time analysis for fixed-priority systems with a write-back cache

2018

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This paper introduces analyses of write-back caches integrated into response-time analysis for fixed-priority preemptive and non-preemptive scheduling. For each scheduling paradigm, we derive four different approaches to computing the additional costs incurred due to write backs. We show the dominance relationships between these different approaches and note how they can be combined to form a single state-of-the-art approach in each case. The evaluation explores the relative performance of the different methods using a set of benchmarks, as well as making comparisons with no cache and a write-through cache. We also explore the effect of write buffers used to hide the latency of write-through caches. We show that depending upon the depth of the buffer used and the policies employed, such buffers can result in domino effects. Our evaluation shows that even ignoring domino effects, a substantial write buffer is needed to match the guaranteed performance of write-back caches.

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“…Xu et al [41] extended multi-core compositional analysis to incorporate cache interference delay caused by private caches, assuming that there is no shared cache. Lunniss et al [42] extended CRPD analysis to a single-core hierarchical scheduling environment. However, none of these approaches focuses on a shared cache in a multi-core platform.…”

Section: Related Workmentioning

confidence: 99%

Towards Predictable Real-Time Performance on Multi-Core Platforms

Kim¹

2016

Preprint

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Cyber-physical systems (CPS) integrate sensing, computing, communication and actuation capabilities to monitor and control operations in the physical environment. A key requirement of such systems is the need to provide predictable real-time performance: the timing correctness of the system should be analyzable at design time with a quantitative metric and guaranteed at runtime with high assurance. This requirement of predictability is particularly important for safety-critical domains such as automobiles, aerospace, defense, manufacturing and medical devices.The work in this dissertation focuses on the challenges arising from the use of modern multi-core platforms in CPS. Even as of today, multi-core platforms are rarely used in safety-critical applications primarily due to the temporal interference caused by contention on various resources shared among processor cores, such as caches, memory buses, and I/O devices. Such interference is hard to predict and can significantly increase task execution time, e.g., up to 12× on commodity quad-core platforms. To address the problem of ensuring timing predictability on multi-core platforms, we develop novel analytical and systems techniques in this dissertation. Our proposed techniques theoretically bound temporal interference that tasks may suffer from when accessing shared resources. Our techniques also involve software primitives and algorithms for real-time operating systems and hypervisors, which significantly reduce the degree of the temporal interference. Specifically, we tackle the issues of cache and memory contention, locking and synchronization, interrupt handling, and access control for computational accelerators such as general-purpose graphics processing units (GPGPUs), all of which are crucial to achieving predictable real-time performance on a modern multi-core platform. Our solutions are readily applicable to commodity multi-core platforms, and can be used not only for developing new systems but also migrating existing applications from single-core to multi-core platforms. vi This dissertation would have been impossible without the help and support of many people. First and foremost, I would like to thank my advisor, Prof. Raj Rajkumar. I was lucky to work with Raj. His guidance and expertise have made me a better thinker, writer, and researcher. Raj gave me opportunities to participate in exciting projects, demonstrate my research results, and mentor other students, all of which led me to become an independent researcher and to pursue an academic career. I am grateful to the members of my thesis committee, Prof. Onur Mutlu, Prof. Anthony Rowe, and Dr. Shige Wang for their time, effort and inputs in completing this dissertation. Thanks to Onur for his insights on various aspects of my work. I learned a lot from Onur on computer architectures, which was a great asset for my research. Thanks to Anthony for his feedback and advice, even since my very early days at CMU. I enjoyed lively conversations with Anthony and liked to hear his view on cyber-physical...

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Accounting for Cache Related Pre-emption Delays in Hierarchical Scheduling

Cited by 11 publications

References 20 publications

Integrated Analysis of Cache Related Preemption Delays and Cache Persistence Reload Overheads

Integrated Analysis of Cache Related Preemption Delays and Cache Persistence Reload Overheads

Response-time analysis for fixed-priority systems with a write-back cache

Towards Predictable Real-Time Performance on Multi-Core Platforms

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