Accuracy improvement of electrical characteristics estimation for sub-20nm FDSOI devices with non-rectangular gates

Cai, Jia-Syun; Chien, Shih‐Chang; Zheng, Xinqian; Lee, Chien-Lin; Tsai, Kuen-Yu

doi:10.1117/12.2515186

Cited by 1 publication

(2 citation statements)

References 8 publications

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“…In this work, we will discuss the accuracy of different EGL methods without LDWFs since extracting weights of many channel widths is time-consuming and still in progress. [11] 3D…”

Section: 4 Location-dependent Weighting Factors Methodsmentioning

confidence: 99%

“…The conventional EGL method did not consider the narrow-width related edge effects [3] , which cannot accurately estimate the performance of the NRG circuits, especially in the sub-threshold characteristic analysis. The location-dependent weighting factors [11] are indispensable to compensate for the current variation.…”

Section: Impacts Of Narrow Width Effects On Electronic Characteristicsmentioning

confidence: 99%

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A transistor sizing method for standard-cell optimization considering lithography effects

Cai,

Su,

Lee

et al. 2024

DTCO and Computational Patterning III

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In modern digital integrated-circuit designs, standard-cell libraries are critical foundations. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. The conventional equation-based approaches can cause significant electric characteristic deviation, and the simulation-based approaches may be severely restricted by initial values. Recently, we proposed an improved transistor sizing method to compensate for the drawbacks. However, it did not consider the layout-dependent lithography effects. The printed wafer patterns can suffer from significant geometric distortions when layout geometry shrinks. It is worth investigating the lithography effects to ensure that the electrical characteristics of the manufactured devices can still meet the target design specifications. This work extends the effectiveness verification of the improved transistor sizing method by further considering the lithography effects. An in-house lithography simulation tool is utilized to generate wafer patterns. The electrical characteristics of transistors with non-rectangular gate shapes due to the lithography distortion are analyzed through different equivalent-gate-length estimation methods. The impacts of lithography effects on the optimized transistor sizes are characterized in several design cases.

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“…In this work, we will discuss the accuracy of different EGL methods without LDWFs since extracting weights of many channel widths is time-consuming and still in progress. [11] 3D…”

Section: 4 Location-dependent Weighting Factors Methodsmentioning

confidence: 99%

Section: Impacts Of Narrow Width Effects On Electronic Characteristicsmentioning

confidence: 99%

A transistor sizing method for standard-cell optimization considering lithography effects

Cai,

Su,

Lee

et al. 2024

DTCO and Computational Patterning III

View full text Add to dashboard Cite

show abstract

Accuracy improvement of electrical characteristics estimation for sub-20nm FDSOI devices with non-rectangular gates

Cited by 1 publication

References 8 publications

A transistor sizing method for standard-cell optimization considering lithography effects

A transistor sizing method for standard-cell optimization considering lithography effects

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