Accuracy of overlay measurements: tool and mark asymmetry effects

Starikov, Alexander; Coleman, Daniel J.; Larson, Patricia J.; Lopata, Alexander D.; Muth, William A.

doi:10.1117/12.56172

Cited by 13 publications

(4 citation statements)

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“…Tool-induced shift is a measure of the effects of tool asymmetry on the measured overlay offset [8]. A TIS correction is ordinarily applied to the measured overlay resulting in TIS-corrected mean.…”

Section: Evaluating Tis and Wismentioning

confidence: 99%

Calibration strategies for overlay and registration metrology

Silver¹,

Stocker²,

Attota³

et al. 2003

SPIE Proceedings

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Critical dimensions in current and next generation devices are driving the need for tighter overlay registration tolerances and improved overlay metrology tool accuracy and repeatability. Tool matching, performance evaluation, model-based metrology, and a move towards closed-loop image placement control all increase the importance of improved accuracy and calibration methodology. The National Institute of Standards and Technology (NIST) is introducing a calibrated overlay wafer standard. A number of calibration requirements must be addressed when using this standard, including identification of the best methods for evaluating measurement bias and uncertainties, proper data acquisition and analysis, and the best calibration strategy.

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Section: Evaluating Tis and Wismentioning

confidence: 99%

Calibration strategies for overlay and registration metrology

Silver¹,

Stocker²,

Attota³

et al. 2003

SPIE Proceedings

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“…[8][9][10] Tool-induced shift (TIS) is evaluated to estimate the impact of tool asymmetry on measurement error. 11 TIS can be obtained by measuring overlay at 0 deg and 180 deg of wafer rotation and the difference of the two divided by 2. Once an estimate of TIS is available, this error can be removed from OL measurement, improving overlay metrology accuracy and tool-to-tool matching.…”

Section: Introductionmentioning

confidence: 99%

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Ito

Hasumi

2019

J. Micro/Nanolith. MEMS MOEMS

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Overlay control has been one of the most critical issues for manufacturing of leading edge semiconductor devices. Introduction of the double patterning process requires stringent overlay control. Conventional optical overlay (Opt-OL) metrology has technical challenges with measurement robustness, solving overlay discrepancy between overlay mark and device pattern, and measuring smaller marks laid out in large numbers within the die accurately for high-order correction. In contrast, scanning electron microscope-based overlay (SEM-OL) metrology can directly measure both overlay targets and actual devices or device-like structures on processed wafers with high spatial resolution. It can be used for reference metrology and optimization of Opt-OL measurement conditions. SEM-OL uses small structures, including actual device patterns, which allows insertion of many SEM-OL targets across a die. Precise overlay distribution can be measured using dedicated SEM-OL mark, improving measurement accuracy and repeatability. To extend SEM-OL capability, we have been developing SEM-OL techniques that can measure not only surface patterns by critical dimension SEM but also buried patterns for leading edge device processes. There are two techniques to detect buried patterns. One is to use high-acceleration voltage SEM, which detects backscattering electron emphasizing material contrast. It has been adopted for overlay measurements for memory and logic devices at after-etch inspection or even after-develop inspection. The other is to utilize charging effect, which reflects voltage contrast at the surface depending on the material properties of underneath structure. SEM-OL measurement using transient voltage contrast has been developed and its capability of overlay measurement has been proven. An overlay measurement algorithm using template matching method has been developed and was applied to dynamic random access memory (DRAM) process monitor in manufacturing. In order to extend SEM-OL metrology to beyond 3-nm node logic and cutting-edge DRAM devices (half pitch = 14 nm), we are improving measurement precision of detecting buried patterns and measurement throughput by developing optimized SEM-OL mark.

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“…General methods in metrology of image placement were established in the early '90s [1][2][3][4][5]. The basic principles were summarized in a "Program Paper" [2] with expectation that each of its three authors would then produce closely related metrology applications with three different equipment vendors: BioRad Q+ overlay metrology system, Carl Suss XLS proximity X-ray stepper alignment system and Prometrix ConQuest2000 linewidth and overlay metrology system.…”

Section: Methods For Metrology Of Image Placement Error Diagnostics Amentioning

confidence: 99%

“…Any definition of centerline for use in microlithography must stem from the same definition of edge. Referring to Figure 3, we define [5,20] the centerline as an average coordinate of two opposing edges, that is, CL = (X1 + X2) / 2. SEMI definition of linewidth [21], due to Nyyssonen and Larrabee [6], specifies the linewidth (LW, CD) as the distance between two opposite line edges in the thin film material with coordinates X1 and X2 LW = | X1 -X2 |.…”

Section: Top Three Applications: Pdr Compliance Process Monitors Andmentioning

confidence: 99%

Applications of image diagnostics to metrology quality assurance and process control

Allgair

Boksha²,

Bunday³

et al. 2003

SPIE Proceedings

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The purpose of this paper is to define standard methods for effective and efficient image-based dimensional metrology for microlithography applications in the manufacture of integrated circuits. This paper represents a consensual view of the co-authors, not necessarily in total agreement across all subjects, but in complete agreement on the fundamentals of dimensional metrology in this application. Fundamental expectations in the conventional comparison-based metrology of width are reviewed, with its reliance on calibration and standards, and how it is different from metrology of pitch and image placement. We discuss the wealth of a priori information in an image of a feature on a mask or a wafer. We define the estimates of deviations from these expectations and their applications to effective detection and identification of the measurement errors attributable to the measurement procedure or the metrology tool, as well as to the sample and the process o fits manufacture. Although many individuals and organizations already use such efficient methods, industrywide standard methods do not exist today. This group of professionals expects that, by placing de facto standard methodologies into public domain, we can help reduce waste and risks inherent in a "spontaneous" technology build-out, thereby enabling a seamless proliferation of these methods by equipment vendors and users of dimensional metrology. Progress in this key technology, with the new dimensional metrology capabilities enabled, leads to improved performance and yield of IC products, as well as increased automation and manufacturing efficiency, ensuring the long-term health of our industry.

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Accuracy of overlay measurements: tool and mark asymmetry effects

Cited by 13 publications

References 0 publications

Calibration strategies for overlay and registration metrology

Calibration strategies for overlay and registration metrology

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Applications of image diagnostics to metrology quality assurance and process control

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