Accurate analog/RF BIST evaluation based on SVM classification of the process parameters

Bounceur, Ahcène; Brahmi, Belkacem; Beznia, Kamel; Euler, Reinhardt

doi:10.1109/idt.2014.7038587

Cited by 3 publications

(7 citation statements)

References 11 publications

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“…4 shows, fixing α and moving the resulting expectation of w into the design matrix (i.e. converting Φu in (14) to Φ in (13)) will reduce every column in Fig. 4 to a single weight vj with its prior βj.…”

Section: Efficient Training Algorithmmentioning

confidence: 99%

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Relevance vector and feature machine for statistical analog circuit characterization and built-in self-test optimization

Lin

2016

Proceedings of the 53rd Annual Design Automation Conference

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Aiding design and test optimization of analog circuits requires accurate models that can reliably capture complex dependencies of circuit performances on essential circuit and device parameters, and test signatures. We present a novel Bayesian learning technique, namely relevance vector and feature machine (RVFM), for characterizing analog circuits with sparse statistical regression models. RVFM not only produces accurate models learned from a moderate amount of simulation or measurement data, but also computes a probabilistically inferred weighting factor quantifying the criticality of each parameter as part of the overall learning framework, hence offering a powerful enabler for variability modeling, failure diagnosis, and test development. Compared to other popular learning-based techniques, the proposed RVFM produces more accurate models, requires less amount of training data, and extracts more reliable parametric ranking. The effectiveness of RVFM is demonstrated in terms of the statistical variability modeling of a low-dropout regulator (LDO) and the built-in self-test (BIST) development of a charge-pump phase-locked loop (PLL).

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Section: Efficient Training Algorithmmentioning

confidence: 99%

“…the CP and VCO quiescent currents, in the quiescent mode. Recently, learning-based classifiers like the SVM have been trained to perform the failure detection in BIST [11,14]. To make better usage of the collected test signatures, we apply the proposed RVFM in each scheme.…”

Section: Pll Bist Scheme Optimizationmentioning

confidence: 99%

Relevance vector and feature machine for statistical analog circuit characterization and built-in self-test optimization

Lin

2016

Proceedings of the 53rd Annual Design Automation Conference

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“…Alternate testing techniques require a mapping between the specification space and the measure space in order to allow the test decision to be performed. Machine learning techniques [9], [10] and regression techniques [5] have been used with successful results to this purpose, as well as using octrees to represent the pass/fail regions [11], [12]. Test costs are heavily raised up due to the existence of decision errors.…”

Section: Introductionmentioning

confidence: 99%

Analog circuits testing using digitally coded indirect measurements

Gómez-Pau

Balado

Figueras

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Testing mixed-signal circuits is a challenging task requiring high amounts of human and technical resources. To overcome these drawbacks, indirect testing methods have been adopted as an efficient solution to perform specification based tests using easy to measure CUT information. In this work, the acceptance/rejection regions are encoded using octrees with arbitrary precision regardless of the complexity of the boundary separating these regions. The strategy relies on two phases: (1) A statistical training phase generates the circuit samples to encode the acceptance/rejection regions using octrees. (2) The testing phase corresponds to the actual production testing of the fabricated ICs. The first phase is performed only once and requires sufficient samples of each pass/fail region to generate the octree under realistic CUT variations. The second phase is fast and only requires to evaluate the octree using the measures of the tested IC. In order to illustrate the proposal, the method has been applied to test a band-pass Biquad filter. Successful simulation results are reported showing considerable advantages in terms of test application time.Postprint (published version

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“…The estimation of the Yield LossŶ L is given by the proportion of the good circuits that fail the test (the black points that are in the white zone) with respect to the total number of the good circuits (the black points). Thus,Ŷ L = 2 4 . The evaluation of these test metrics with high precision, at ppm (parts per million) level, can be done just with a very large sample of circuits.…”

mentioning

confidence: 99%

“…So there is a requirement to develop alternative test approaches for classifying the circuits into pass and fail categories without performing their intended specifications. Some creative binary classification techniques, such as Support Vector Machines (SVM) and Artificial Neural Networks (ANN) have been successfully applied to fault diagnosis for analog circuits [2].…”

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confidence: 99%

A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

et al. 2018

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Specifications of Radio Frequency (RF) analog integrated circuits have increased strictly as their applications tend to be more complicated and high test cost demanding. This makes them very expensive due to an increased test time and to the use of sophisticated test equipment. Alternative test measures, extracted by means of Built-In Self Test (BIST) techniques, are useful approaches to replace standard specification-based tests. One way to evaluate the efficiency of the CUT measures at the design stage is by estimating the Test Escapes (T E) and the Yield Loss (Y L) at ppm level. Unfortunately, an important number of Monte Carlo simulations must be run in order to guarantee their accuracy. For certain types of circuits, this requires many months or even years to generate millions of circuits. To overcome this limitation, we present in this paper a new technique where a small number of simulations is sufficient to reach an important precision. This method is based on a classification using machine learning methods, such as SVM and Neural Networks based classifiers to determine pass/fail regions. The proposed approach requires a few number of simulations only to determine the region separating the process parameters generating good and faulty, or pass and fail circuits. Then only this region is needed to estimate the test metrics without running any additional simulation. The proposed methodology is illustrated for the evaluation of a filter BIST technique. Keywords Analog/RF test • SVM classification • Neural Network classification • BIST evaluation 1 Introduction The test is a very important notion in the field of the validation step of analog circuit design. It is the way to confirm whether a circuit under test (CUT) satisfies all functional specifications that represent its performance parameters. Since there are no manufactured circuits at the design stage, test errors can only be

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Accurate analog/RF BIST evaluation based on SVM classification of the process parameters

Cited by 3 publications

References 11 publications

Relevance vector and feature machine for statistical analog circuit characterization and built-in self-test optimization

Relevance vector and feature machine for statistical analog circuit characterization and built-in self-test optimization

Analog circuits testing using digitally coded indirect measurements

A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

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