Accurate analytical modeling of junctionless DG-MOSFET by green's function approach

Nandi, Ashutosh; Pandey, Nilesh

doi:10.1016/j.spmi.2017.07.062

Cited by 15 publications

(2 citation statements)

References 19 publications

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“…Furthermore, at nanodevice level, junctionless (JL) transistors are the best alternate to solve the problem of sharp junctions associated with conventional transistors. Moreover, JL field effect transistors (FETs) are also admired to suppress the SCEs further [9][10][11].…”

Section: Introduction: According To the International Technologymentioning

confidence: 99%

Performance analysis of junctionless DG‐MOSFET‐based 6T‐SRAM with gate‐stack configuration

Tayal

Nandi

2018

Micro & Nano Letters

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In this work, the investigation of high-K gate-stack-based junctionless (JL) double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is carried out to study the high-K gate dielectric effect on six-transistor (6T)-static random-access memory (SRAM) built with JLDG-MOSFET. It is observed that the utilisation of the high-K gate dielectric in JLDG-MOSFETs improves the static noise margin (SNM) that is the stability of the cell as well as access time (AT) which reflects the delay performance of the SRAM cell. Furthermore, scaling down of L g degrades the stability. Moreover, it is also described that the enhancement in hold SNM (ΔHSNM = HSNM (K=40) −HSNM (K=3.9)), read SNM (ΔRSNM = RSNM (K=40) −RSNM (K=3.9)), and write SNM (ΔWSNM = WSNM (K=40) −WSNM (K=3.9)) is restricted at lower L g without much enhancement in the improvement of read AT and write AT. Therefore, it is appropriate to consider higher channel length (∼30 nm) while designing high-K gate-stacked-based JLDG-MOSFETs for the 6T-SRAM cell.

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Section: Introduction: According To the International Technologymentioning

confidence: 99%

Performance analysis of junctionless DG‐MOSFET‐based 6T‐SRAM with gate‐stack configuration

Tayal

Nandi

2018

Micro & Nano Letters

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“…Another problem with these models is that it takes a long time to complete the simulation. 18,19,21 Using artificial neural networks (ANN) is one of the effective ways and provide to reduce the complexity of semiconductor-based modeling tools, which consists of a number of neurons whose weights are updated according to the specific purpose, and finally, any complex nonlinear function can be modeled. This method has been investigated in many semiconductor structures and introduced as one of the efficient techniques.…”

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confidence: 99%

Graphene Nanoribbon FET Compact Model on the Basis of ANN Configuration Applicable in Different Spice Levels

Anvarifard

Ramezani

Amiri

2021

ECS J. Solid State Sci. Technol.

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The artificial neural networks (ANNs) are widely utilized as a powerful approximator for a vast number of complicated nonlinear functions in many fields in different domains. Multi-layer perceptron (MLP) as a unique strategy in this work has been highlighted making an analytical drain current prediction of graphene nanoribbon field-effect transistor (GNRFET) simple and efficient having a linear dependence on the fundamental variables. The MLP structure in this work is configured with three hidden layers and 5-dimensional inputs giving the best result after performing different experiments. Target output as the key parameter is actually the numerically calculated drain current by the Non-Equilibrium Green Function (NEGF) method which is commonly used for the simulation of nanoscale devices. The critical parameters in the cases of gate oxide thickness, gate length, number of carbon atoms across the channel, gate voltage, and drain voltage are selected as the dimensions of the input vector impacting the obtained drain current by the ANN. The comprehensive comparison between the NEGF approach and the proposed ANN-based model revealed an excellent match and correlation between them. As a result, this model can be taken into consideration as a suitable tool in the different spice levels owing to the saving the running time and also increase in the efficiency of nanoscale circuits based on the GNRFET structure.

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A nanoscale junctionless FET to amend the electric field distribution using a β-Ga2O3 packet

Heidari,

Orouji,

Bozorgi

2023

J Mater Sci: Mater Electron

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Accurate analytical modeling of junctionless DG-MOSFET by green's function approach

Cited by 15 publications

References 19 publications

Performance analysis of junctionless DG‐MOSFET‐based 6T‐SRAM with gate‐stack configuration

Performance analysis of junctionless DG‐MOSFET‐based 6T‐SRAM with gate‐stack configuration

Graphene Nanoribbon FET Compact Model on the Basis of ANN Configuration Applicable in Different Spice Levels

A nanoscale junctionless FET to amend the electric field distribution using a β-Ga2O3 packet

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