Accurate capture of timing parameters in inductively-coupled on-chip interconnects

Abstract

With continuously increasing on-chip frequencies and shortening signal rise time, inductance effects pose sever difficulties on efficient timing analysis. This work analyses the effects on different timing parameters of the inductive coupling in long and intermediate high-frequency on-chip interconnects. We show that crosstalk, noise, signal integrity, signal rise and fall times, all depend on the data toggling pattern. Moreover, the conclusion is drawn that the worst and best case switching patterns are not necessarily similar for capacitively coupled dominant and for mainly inductively coupled lines.