Accurate determination of ultrathin gate oxide thickness and effective polysilicon doping of CMOS devices

Abstract

Abstract-We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25Å) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C0V ) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments.

Controlled charge trapping by molybdenum disulphide and graphene in ultrathin heterostructured memory devices

“…Even though the dielectric strength in this device is smaller than the reported value (8 MV cm À 1 ; ref. 7), high-temperature treatment-like annealing process can lower the dielectric strength of hBN by generating defects 44 . As the annealing temperature increases, tunnelling current through hBN was enhanced probably by trap-assisted tunnelling.…”

Conductive atomic force microscopy as a tool to reveal high ionising dose effects on ultra thin SiO2/Si structures

“…where E ox is the electric field into the oxide and C and v are constants depending on the oxide characteristics, equals to C = 9.92 9 10 -7 A V -2 and v = 2.635 9 10 8 V for SiO 2 (Gupta et al 1997). E ox is given by E ox = V ox /T ox where V ox is the effective voltage in the oxide and T ox is the oxide thickness.…”

“…E ox is given by E ox = V ox /T ox where V ox is the effective voltage in the oxide and T ox is the oxide thickness. V ox can be related to the density of trapped charges DN using the following relation (Gupta et al 1997):…”

Mechanisms of dc-current transfer in tris(acetylacetonato)iron(III) films

“…It is not high enough to pin the Fermi level of the Si substrate [12]. The C(V g ) curve is used to determine the insulator voltage V ins in terms of gate voltage V g [7][8][9]. We mention that charges Q ins are considered as trap centers that control the dc-conduction process and that determine the mechanism controlling the current transfer in that insulator.…”