Accurate operation delay prediction for FPGA HLS using graph neural networks

Ustun, Ecenur; Deng, Chonghai; Pal, Debjit; Li, Zhijing; Zhang, Zhiru

doi:10.1145/3400302.3415657

Cited by 55 publications

(13 citation statements)

References 20 publications

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“…They first employ an automated hardware optimization tool to achieve the optimized metrics of the register-transfer level code, which is generated by a high-level synthesis tool, and then compose the training data set to employ in learning model to estimate the accurate design metrics. To increase the mapping efficiency of arithmetic operations on hardened blocks of FPGAs, Usten et al propose to use graph neural network to automatically learn and extract the clustering pattern and operation mapping [34]. The training data is collected using the results of technology mapping of a set of microbenchmarks composed of arithmetic operations.…”

Section: B Utilizing ML Approaches To Increase the Efficiency Of Fpga Designsmentioning

confidence: 99%

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

2021

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Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the FPGAs with power-gating ability is a promising way to effectively address the power-consumption obstacle. However, the main challenge when implementing power gating is in choosing the clusters of resources in a way that would allow the most power-saving opportunities. In this paper, we take advantage of machine learning approaches, such as K-means clustering, to propose efficient algorithms for creating power-gating clusters of FPGA routing resources. In the first group of proposed algorithms, we employ K-means clustering and exploit the utilization pattern of routing resources. In the second group of algorithms, we enhance the power-gating efficiency by minimizing the power overhead introduced by power-gating logic and by taking into account the size of routing multiplexers, which influences the power-gating efficiency. Finally, we enhance and further develop the baseline FPGA routing algorithm to be aware and take advantage of power gating opportunities. The experimental results on Titan benchmark suite and the latest Intel Stratix-IV FPGA architecture in VTR 8.0 show that our approaches achieve an improvement of about 70%, on average, in reducing the FPGA static power consumption over the best power-gating approaches proposed in the previous studies.INDEX TERMS Field-programmable gate arrays, static power consumption, power gating, routing algorithm, machine learning

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Section: B Utilizing ML Approaches To Increase the Efficiency Of Fpga Designsmentioning

confidence: 99%

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

2021

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“…ML techniques have been applied to improve HLS tools from the following three aspects: fast and accurate result estimation [30,37,105,106,140,161,169], refining conventional DSE algorithms [74,104,146], and reforming DSE as an active-learning problem [92,93,109,177]. In addition to achieving good results on individual problems, previous studies have also introduced new generalizable techniques about feature engineering [30,105,106,161,169], selection and customization of ML models [140], and design space sampling and searching strategies [93,109,177].…”

Section: High Level Synthesismentioning

confidence: 99%

“…ML techniques have been applied recently to reduce the HLS tool's prediction error of the operation delay [140]. Existing HLS tools perform delay estimations based on the simple addition of pre-characterized delays of individual operations, and can be inaccurate because of the post-implementation optimizations (e.g., mapping to hardened blocks like DSP adder cluster).…”

Section: Inaccuratementioning

confidence: 99%

“…Gaussian Process [37] Operation delay Graph Neural Network [140] Cross-platform Predict for new FPGA platforms ANN [106] Predict for new applications through executing on CPUs Linear models, ANN, Random Forest [113] Active learning…”

Section: Latencymentioning

confidence: 99%

“…of the model. For example, Ustun et al [140] customize a standard GNN model to handle the specific delay prediction problem, which brings extra benefit in model accuracy.…”

Section: Summary Of Machine Learning For Hlsmentioning

confidence: 99%

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Machine Learning for Electronic Design Automation: A Survey

Huang

et al. 2021

Preprint

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With the down-scaling of CMOS technology, the design complexity of very large-scale integrated (VLSI) is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 90s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interests in incorporating ML to solve EDA tasks. In this paper, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.

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