Accurate prediction of detailed routing congestion using supervised data learning

Qi, Zhongdong; Cai, Yici; Zhou, Qiang

doi:10.1109/iccd.2014.6974668

Cited by 54 publications

(18 citation statements)

References 15 publications

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“…A fast global routing algorithm is integrated in placement and its result is used to estimate routability. However, recent researches [6][7][8][9][10] indicate that there is a gap between global routing and detailed routing. A design with little overflow after global routing may end up as unroutable after detailed routing.…”

Section: Introductionmentioning

confidence: 99%

An accurate detailed routing routability prediction model in placement

Zhou

Wang

et al. 2015

2015 6th Asia Symposium on Quality Electronic Design (ASQED)

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Routability is one of the primary objectives in placement. There have been many researches on forecasting routing problems and improving routability in placement but no perfect solution is found. Most traditional routability-driven placers aim to improve global routing result, but true routability lies in detailed routing. Predicting detailed routing routability in placement is extremely difficult due to the complexity and uncertainty of routing. In this paper, we propose a new detailed routing routability prediction model based on supervised learning. After extracting key features in placement and detailed routing, multivariate adaptive regression is performed to train the connection between these two stages. Using a well-trained model, most design rule violations after detailed routing can be foreseen in placement stage. Experiments show that our average prediction accuracy is 79.8%, which is comparable with other state-of-art routability estimation techniques.

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Section: Introductionmentioning

confidence: 99%

An accurate detailed routing routability prediction model in placement

Zhou

Wang

et al. 2015

2015 6th Asia Symposium on Quality Electronic Design (ASQED)

Self Cite

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“…Several pioneering work attempted to enhance FPGA design-automation algorithms through optimizing their parameters with the help of ML approaches [18]- [22]. Furthermore, several studies employ ML techniques to improve the quality of congestion estimation in the placement and routing steps of the design automation process [23]- [26]. To the best of our knowledge, none of the previous studies have attempted to apply an ML-inspired approach to design power gating regions for the FPGA routing network in order to reduce the FPGA static power consumption.…”

Section: Introductionmentioning

confidence: 99%

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

2021

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Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the FPGAs with power-gating ability is a promising way to effectively address the power-consumption obstacle. However, the main challenge when implementing power gating is in choosing the clusters of resources in a way that would allow the most power-saving opportunities. In this paper, we take advantage of machine learning approaches, such as K-means clustering, to propose efficient algorithms for creating power-gating clusters of FPGA routing resources. In the first group of proposed algorithms, we employ K-means clustering and exploit the utilization pattern of routing resources. In the second group of algorithms, we enhance the power-gating efficiency by minimizing the power overhead introduced by power-gating logic and by taking into account the size of routing multiplexers, which influences the power-gating efficiency. Finally, we enhance and further develop the baseline FPGA routing algorithm to be aware and take advantage of power gating opportunities. The experimental results on Titan benchmark suite and the latest Intel Stratix-IV FPGA architecture in VTR 8.0 show that our approaches achieve an improvement of about 70%, on average, in reducing the FPGA static power consumption over the best power-gating approaches proposed in the previous studies.INDEX TERMS Field-programmable gate arrays, static power consumption, power gating, routing algorithm, machine learning

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“…Machine learning has become pervasive in various research fields and commercial applications, and achieved satisfactory products [12]. Supervised learning is employed to detect detailed routing violations [13,14,15]. A machine learning framework is proposed to predict detailed routing short violations just from a placed netlist [16].…”

Section: Introductionmentioning

confidence: 99%

A local congestion elimination technique driven by overflow

Shi

et al. 2020

IEICE Electron. Express

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In the physical design of VLSI circuits, the congestion generated in placement stage tends to enlarge the total wirelength (TWL) and further worsens the timing and routability. In this letter, a local congestion elimination technique is proposed which can be compatible with available commercial P&R EDA tools. Driven by overflow value, the optimal keepout margins being added around the highest pin cells in specific congestion regions are searched using simulated annealing (SA) algorithm and ant colony optimization (ACO) algorithm respectively to ameliorate local congestion. Experimental results have shown that the proposed technique can reduce the design rule violations (DRV), shorts and TWL significantly.

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Accurate prediction of detailed routing congestion using supervised data learning

Cited by 54 publications

References 15 publications

An accurate detailed routing routability prediction model in placement

An accurate detailed routing routability prediction model in placement

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

A local congestion elimination technique driven by overflow

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