Accurate Time-Domain Simulation of Continuous-Time Sigma–Delta Modulators

Bénabès, Philippe

doi:10.1109/tcsi.2008.2012224

Cited by 5 publications

(4 citation statements)

References 25 publications

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“…7, where the frond-end (CT) stage is sampled at and the remaining stages are sampled at . In this case, following the same procedure as in previous sections, it can be shown that the -transform of the modulator output is given by (16) where is the quantization error of the -stage and (17) As an illustration, Fig. 8(a) where NTF , NTF , and STF STF .…”

Section: Extension To Generic N-stage Cascade Ds Mr Ms the Conceptmentioning

confidence: 99%

“…1 can be carried out in the -domain by applying a CT-to-DT transformation to the front-end stage. The resulting DT M is equivalent to the original M. This CT-to-DT equivalence can be guaranteed because of the DT nature of the (open) loop transfer function from the front-end quantizer output to the sampled quantizer input [1], [16], [17]. Assuming a linear model for the quantizers in Fig.…”

Section: Introductionmentioning

confidence: 99%

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Multirate Downsampling Hybrid CT/DT Cascade Sigma-Delta Modulators

Garcia-Sanchez

Rosa

2012

IEEE Trans. Circuits Syst. I

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Section: Extension To Generic N-stage Cascade Ds Mr Ms the Conceptmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Multirate Downsampling Hybrid CT/DT Cascade Sigma-Delta Modulators

Garcia-Sanchez

Rosa

2012

IEEE Trans. Circuits Syst. I

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“…Based on the impulse-invariant transform [19] and the DT model of a CT SDM [20], the CT path from to the sampler output in Fig. 2(b) can be replaced by an equivalent DT circuit.…”

Section: B Proposed Sdm With a Fast Tracking Quantizermentioning

confidence: 99%

Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators

Colodro

Torralba

2010

IEEE Trans. Circuits Syst. I

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Using a tracking analog-to-digital converter as the quantizer of a sigma-delta modulator (SDM) has been shown to be an efficient method of reducing the number of comparators. In this paper, a new continuous-time (CT) SDM is proposed where a large reduction in the number of comparators is obtained by clocking the quantizer tracking loop at a high frequency rate. For a given example, the number of bits of the quantizer is shown to be reduced from five in the original multibit modulator to only one in a quantizer with tracking sampled at three times the original sampling frequency. In addition, the output of the tracking quantizer can be downsampled so that the modulator output has the same resolution and sampling rate as the original modulator. In this way, the design of the digital-to-analog converters in the feedback loop and the decimator filter at the modulator output are not penalized. Furthermore, the digital integrator of the tracking loop can be removed by taking profit of the last CT integrator in the forward path. Finally, the signal component in the forward path can be attenuated by adding a direct path from the modulator input to the last integrator input. As a result, the output swing of the integrators is reduced, improving the linearity of the whole modulator. The new modulators are analyzed and extensive theoretical and simulation results are provided.

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“…The resulting MR H-Σ∆M is equivalent to the original MR DT-Σ∆M. This CT-DT equivalence can be guaranteed because of the DT nature of the (open) loop transferfunction from the front-end quantizer output to the sampled quantizer input[12,13].…”

mentioning

confidence: 97%

Efficient hybrid continuous-time/discrete-time cascade ΣΔ modulators for wideband applications

Garcia-Sanchez

Rosa

2014

Microelectronics Journal

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This paper analyses the use of hybrid continuous-time/discrete-time cascade Σ∆ modulators for the implementation of power-efficient analog-to-digital converters in broadband wireless communication systems. Two alternative implementations of multi-rate cascade architectures are studied and compared with conventional single-rate continuous-time topologies, taking into account the impact of main circuit-level error mechanisms, namely: mismatch, finite dc gain and gainbandwidth product. In all cases, closed-form design equations are derived for the nonideal in-band noise power of all Σ∆ modulators under study, providing analytical relationships between their system-level performance and the corresponding circuit-level error parameters. Theoretical predictions match simulation results, showing that the lowest performance degradation is obtained by a new kind of multi-rate hybrid Σ∆ modulator, in which the front-end (continuous-time) stage operates at a higher rate than the back-end (discrete-time) stages. As a case study, the design of a hybrid GmC/switched-capacitor fourth-order (two-stage, 4bit) cascade Σ∆ modulator is discussed to illustrate the potential benefits of the presented approach 1 .

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Accurate Time-Domain Simulation of Continuous-Time Sigma–Delta Modulators

Cited by 5 publications

References 25 publications

Multirate Downsampling Hybrid CT/DT Cascade Sigma-Delta Modulators

Multirate Downsampling Hybrid CT/DT Cascade Sigma-Delta Modulators

Continuous-Time Sigma–Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators

Efficient hybrid continuous-time/discrete-time cascade ΣΔ modulators for wideband applications

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