Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning

Hyun, Daijoon; Fan, Yuepeng; Shin, Youngsoo

doi:10.23919/date.2019.8715016

Cited by 18 publications

(10 citation statements)

References 6 publications

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“…Jeong et al [63] learn a model with MARS to predict performance from a given set of circuit configurations, with NoC router, a specific functional circuit and a specific business tool. In [60], the researchers introduce Linear Discriminant Analysis (LDA) algorithm to find seven combined features for the best representation, and then a KNN-like approach is adopted to combine the prediction results of ANN, SVM, LASSO, and other machine learning models. In this way, Hyun et al [60] improve the wire length prediction given by the virtual placement and routing in the synthesis.…”

Section: Routing Information Predictionmentioning

confidence: 99%

“…In [60], the researchers introduce Linear Discriminant Analysis (LDA) algorithm to find seven combined features for the best representation, and then a KNN-like approach is adopted to combine the prediction results of ANN, SVM, LASSO, and other machine learning models. In this way, Hyun et al [60] improve the wire length prediction given by the virtual placement and routing in the synthesis. Cheng et al [27] predict the final circuit performance in the macro placement stage, and Li and Franzon [81] predict the circuit performance in the global routing stage, including congestion number, hold slack, area and power.…”

Section: Routing Information Predictionmentioning

confidence: 99%

“…MARS [63] To predict wirelength. LDA, KNN [60] To predict the circuit performance after placement stage. ML [27] To predict detailed routing result after global routing.…”

Section: Marssvm [18]mentioning

confidence: 99%

“…The reason why we do not use a discrete action space is because that will lose the relative order information, also because the discrete action space is too large. For instance, for a typical operational amplifier with 20 transistors, each with three parameters, and each size with 1000 value options, the size of the discrete space is about 1000 60 . Reward.…”

Section: Machine Learning For Device Sizing Automationmentioning

confidence: 99%

“…Standard practices like feature normalization and edge data removal are commonly used in the preprocessing stage. Some studies also use dimension reduction techniques like PCA and LDA to further adjust input features [60]. In addition, feature dimension reduction is, by itself, a research topic to reduce test cost in verification (see Section 7).…”

Section: Data Preparationmentioning

confidence: 99%

See 4 more Smart Citations

Machine Learning for Electronic Design Automation: A Survey

Huang

et al. 2021

Preprint

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With the down-scaling of CMOS technology, the design complexity of very large-scale integrated (VLSI) is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 90s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interests in incorporating ML to solve EDA tasks. In this paper, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.

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Section: Routing Information Predictionmentioning

confidence: 99%

Section: Routing Information Predictionmentioning

confidence: 99%

“…MARS [63] To predict wirelength. LDA, KNN [60] To predict the circuit performance after placement stage. ML [27] To predict detailed routing result after global routing.…”

Section: Marssvm [18]mentioning

confidence: 99%

Section: Machine Learning For Device Sizing Automationmentioning

confidence: 99%

Section: Data Preparationmentioning

confidence: 99%

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Machine Learning for Electronic Design Automation: A Survey

Huang

et al. 2021

Preprint

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Net-Based Machine Learning-Aided Approaches for Timing and Crosstalk Prediction

Liang

Xie²,

Barboza³

et al. 2022

Machine Learning Applications in Electronic Design Automation

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Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Cao

Bale

Trefzer

2023

IET Computers & Digital Tech

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Modern electronic design automation (EDA) tools can handle the complexity of state-ofthe-art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independently optimised design step, overheads and inefficiencies can accumulate in the resulting overall design. Performing design-specific optimisation from a more global viewpoint requires more time due to the larger search space but has the potential to provide solutions with improved performanc. In this work, a fully-automated, multi-objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, prior to physical implementation, through MO population-based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is aimed at digital circuit optimisation at the block level, where it is capable of expanding the design space and offers a set of trade-off solutions for different case-specific utilisation. We have applied the proposed multi-objective electronic design automation flow (MOEDA) framework to ISCAS-85 and EPFL benchmark circuits by using a commercial 65 nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow and how simultaneously a significant improvement in PPA metrics is achieved.

show abstract

Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning

Cited by 18 publications

References 6 publications

Machine Learning for Electronic Design Automation: A Survey

Machine Learning for Electronic Design Automation: A Survey

Net-Based Machine Learning-Aided Approaches for Timing and Crosstalk Prediction

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

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