2020
DOI: 10.3390/s20133788
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ACE: ARIA-CTR Encryption for Low-End Embedded Processors

Abstract: In this paper, we present the first optimized implementation of ARIA block cipher on low-end 8-bit Alf and Vegard’s RISC processor (AVR) microcontrollers. To achieve high-speed implementation, primitive operations, including rotation operation, a substitute layer, and a diffusion layer, are carefully optimized for the target low-end embedded processor. The proposed ARIA implementation supports the electronic codebook (ECB) and the counter (CTR) modes of operation. In particular, the CTR mode of operati… Show more

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Cited by 8 publications
(10 citation statements)
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References 16 publications
(66 reference statements)
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“…Since the length of the original word of the ARIA block cipher is 8-bit, the implementation of ARIA is efficient for the 8-bit architecture as described in [2]. However, the 8-bit word-based ARIA architecture is not efficient for 16-bit cases.…”
Section: Proposed Methodsmentioning
confidence: 99%
See 2 more Smart Citations
“…Since the length of the original word of the ARIA block cipher is 8-bit, the implementation of ARIA is efficient for the 8-bit architecture as described in [2]. However, the 8-bit word-based ARIA architecture is not efficient for 16-bit cases.…”
Section: Proposed Methodsmentioning
confidence: 99%
“…LUT#1 3 Optimization of Counter Mode of Operation for 16-bit Architecture: The counter mode of operation can be skipped through pre-computation with constant variables [2]. Previous works have been devoted to improve the performance of counter mode through the precomputation [2,[20][21][22][23][24]. The input of counter mode of operation consists of counter (32-bit) and constant nonce (96-bit).…”
Section: Algorithmmentioning
confidence: 99%
See 1 more Smart Citation
“…In [10], an optimized ARIA block cipher was presented. They optimized primitive operations, including rotation operation, a substitute-layer, and a diffusion-layer on a lowend AVR microcontroller.…”
Section: E Related Workmentioning
confidence: 99%
“…In [14], implementations of AES-GCM achieved 415, 466, and 477 clock cycles per byte for 128-bit, 192-bit, and 256-bit security levels, respectively. In [15], implementations of ARIA-CTR achieved 187.1, 216.8, and 246.6 clock cycles per byte for 128-bit, 192-bit, and 256-bit security levels, respectively.…”
Section: Previous Block Cipher Implementations On 8-bit Avr Microcont...mentioning
confidence: 99%