Achieving 16 Gb/s Single-Ended Signaling in High-Performance Graphics Memory

Hollis, Timothy M.; Brox, M.; Spirkl, W.; Hein, Thomas; Ovard, David; Greeff, Roy; Lin, Dan; Richter, Michael; Mayer, Peter; Moden, Walt; Kuzmenka, Maksim; Balakrishnan, Mani; Ivanov, Milena; Plan, Manfred; Alvarez-Gonzalez, Marcos; Gardiner, Bryce; Lim, Dong Soon; Weller, Jörg

doi:10.1109/wmed.2018.8360835

Cited by 5 publications

(2 citation statements)

References 5 publications

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“…The demand for high-bandwidth DRAMs is constantly increasing due to the datacentric trend [1][2][3]. DRAM bandwidth can be increased by raising the number of I/O pins or the clock frequency [4]. However, double data-rate (DDR), low-power double data-rate (LPDDR), and graphic double data-rate (GDDR) memories have a pin count limitation, so a higher clock frequency is required to increase the data-rate per pin.…”

Section: Introductionmentioning

confidence: 99%

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

et al. 2021

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This paper presents a method for preventing output level distortion while matching the channel impedance in the single-ended PAM-4 transmitter for memory interfaces. ZQ codes for all four output signal levels were obtained through ZQ calibration and saved in the ZQ code table. The ZQ code generator then adaptively selected the appropriate codes depending on the data pattern and delivered them to the output driver; this can improve the level separation mismatch ratio (RLM) while matching the channel impedance. To validate the effectiveness of our approach, a prototype chip with an active area of 0.035 mm2 was fabricated in a 65 nm CMOS process. It achieved the energy efficiency of 3.09 pJ/bit/pin at 18 Gb/s/pin, and its RLM was 0.971 while matching the channel impedance.

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Section: Introductionmentioning

confidence: 99%

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

et al. 2021

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“…The diversity of high-speed I/O standards for DRAM requires an automated way of doing production tests over a variety of channels [1,2,3,4,5,6,7]. DRAM standards, such as DDR4, LPDDR4, GDDR5, and HBM address different application-specific needs in PCs, mobile devices, graphics processors, and artificial intelligence (AI) accelerators, respectively [8,9,10,11], and use different I/O channels whose loss characteristics span a wide variety, as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A channel-emulating high-speed transmitter with pseudo-logarithmic and low-bandwidth amplifiers

Kim

2019

IEICE Electron. Express

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This paper describes a transmitter that can emulate a wide variety of frequency-dependent loss characteristics of high-speed dynamic random-access memory (DRAM) channels, with an aim to facilitate an automated test procedure for a DRAM interface, which does not require physical reconfiguration of channels. Specifically, the proposed transmitter can generate the waveform of an NRZ data stream that has experienced adjustable amounts of skin-effect loss and dielectric loss in electrical channels. To save the hardware cost of implementing a high-speed, high-resolution digital-to-analog converter, the transmitter constructs the waveform using a set of logarithmic and exponential basis functions, each of which is implemented using a pseudo-logarithmic amplifier and lowbandwidth amplifier with adjustable gain and bandwidth, respectively. The prototype chip, fabricated in a 65-nm CMOS process, occupies an area of 5200 µm 2 and operates over 1.4-7 Gbps while dissipating 38 mW at 7 Gbps. It is demonstrated that the implemented transmitter can emulate 10-40"-long microstrip lines on an FR4 grade material with a peak error less than 12.5% in the pulse response.

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Research on Acceleration Technologies and Recent Advances of Data Center GPUs

Cui,

Wu,

et al. 2023

2023 8th International Conference on Intelligent Computing and Signal Processing (ICSP)

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Achieving 16 Gb/s Single-Ended Signaling in High-Performance Graphics Memory

Cited by 5 publications

References 5 publications

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

A channel-emulating high-speed transmitter with pseudo-logarithmic and low-bandwidth amplifiers

Research on Acceleration Technologies and Recent Advances of Data Center GPUs

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