Achieving High-Performance On-Chip Networks With Shared-Buffer Routers

Tran, Anh; Baas, Bevan M.

doi:10.1109/tvlsi.2013.2268548

Cited by 47 publications

(29 citation statements)

References 37 publications

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“…A number of researchers have focused on the design and organization of routers buffers due to its tight relation with the NoC power, performance and area. Some of them have used a complex architecture as compared to conventional VC-based router architecture, or they are efficient under certain NoC configurations or data flow circumstances [19,34,35,36]. Some of these research works are discussed in this section.…”

Section: Buffering Organization Approachmentioning

confidence: 99%

Virtual channel organization and arbitration for network on chip router architecure

Gharan¹

2021

Preprint

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The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the art paradigm for efficient on-chip communication. Among the various components employed in NoC routers, Virtual Channel (VC) plays an important role in the performance and hardware requirements of an NoC system. The VC mechanism enables the multiplexing and buffering of several packets to travel over a single physical channel concurrently. VC arbitration (or arbiter) is another critical organization component of a router that has significant impact on the efficiency of an NoC system. Arbiter performs arbitration among the group of VCs that are competing for a single resource (e.g. output-port). In this dissertation, we propose novel approaches for dynamic VC flow control mechanism and VC arbitration. The first two approaches are based on the adaptivity of VCs in the router input-port that improves the efficiency of NoC system. In both of techniques, the input-port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to a real-time traffic situation. The performance improvement is achieved by utilizing multiple virtual channels with minimal buffer resources. The VC arbitration approach is based on an efficient and fast arbiter that functions upon the index of its input-ports (or VC requests). The architecture of arbiter scales with the Log2 of the number of inputs where a conventional round robin arbiter scales with the number of inputs. The index based behavior and the architecture of our arbiter leads to lower power consumption and chip area. This dissertation presents the organizations and micro-architectures of NoC routers. We have employed SystemVerilog at the micro-architectural level design and modeling of NoC components. We employ three CAD platforms namely ModelSim, Quartus (FPGA) and Synopsys (ASIC level) to design, simulate and implement our router based NoCs. The simulation results support the theoretical concepts of our proposed VC organization and arbitration approaches. We have also implemented and conducted simulation and modeling experiments for conventional VC organization and arbitration models. The experimental results verify the efficiency of our proposed models in terms of power, area and performance in different NoC configurations.

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Section: Buffering Organization Approachmentioning

confidence: 99%

Virtual channel organization and arbitration for network on chip router architecure

Gharan¹

2021

Preprint

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“…This is a lightweight architecture with minimal buffering. In [24], Tran and Baas proposed a shared buffer router (RoShaQ) for high performance NoCs. This architecture optimizes the utilization of buffers.…”

Section: Router Architecture With Shared Queuesmentioning

confidence: 99%

A Routing Algorithm and a Router Architecture for 3d Noc

Somasundaram

Calicut

2019

csci

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In recent years, the enhancement of microchip technologies has enabled large scale Systems-on-Chip (SoC). Due to sharp increase in number of processing elements, SoC faces various challenges in design and testing. Network on Chip (NoC) is an alternative technology to overcome the challenges in SoC design and testing. NoC emerged as a key architecture that allows one to optimize the parameters like power andarea. Inspiteofitsapplications, NoCfacessomerealtimechallengeslikedesigning an optimum topology, routing scheme and application mappings. In this paper, we address the main three issues on NoC, namely, designing of an optimal topology, routing algorithm and a router design for the topology. First, we propose a topology and a routing algorithm. We prove that our recursive network topology is Hamiltonian connected and we propose an algorithm for data packet transmissions, which is free from cyclic deadlocks and the algorithm maximizes the congestion factor. Our experimental results show that the proposed topology gives better performance in terms of average latency and power than the other topologies. Finally, we propose a router architecture for our 3D-NoC. The router architecture is based on shared buffers. Also, our experimental results indicate that the proposed router architecture consumes less area and power than the Virtual Channel architecture.

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“…Meanwhile, interconnection structure also results in a certain amount of power consumption overhead, which passes from the switch unit and data traffic in interconnection structure. Tran proposed a multilayer interconnection structure, which makes long-range processor cores of the mesh interconnection structure directly connected to each other with an additional programmable switch unit [6,7]. The situation of long-range processor cores communicating with each other is avoided through a large number of switch units in traditional mesh interconnection structure.…”

Section: Related Workmentioning

confidence: 99%