Achieving High Performance with FPGA-Based Computing

Abstract

Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmable gate arrays. The challenge is identifying the design techniques that can extract high performance potential from the FPGA fabric.Accelerating high-performance computing (HPC) applications with field-programmable gate arrays (FPGAs) can potentially deliver enormous performance. A thousand-fold parallelism is possible, especially for low-precision computations. Moreover, since control is configured into the logic itself, overhead instructions-such as array indexing and loop computationsneed not be emulated, and every operation can deliver payload.At the same time, using FPGAs presents significant challenges 1 including low operating frequency-an FPGA clocks at one-tenth that of a high-end microprocessor. Another is simply Amdahl's law: To achieve the speedup factors required for user acceptance of a new technology (preferably 50 times), 2 at least 98 percent of the target application must lend itself to substantial acceleration. As a result, HPC/FPGA application performance is unusually sensitive to the implementation's quality.The problem of achieving significant speedups on a new architecture without expending exorbitant development effort, and while retaining flexibility, portability, and maintainability, is a classic one. In this case, accelerating HPC applications with FPGAs is similar to that of porting uniprocessor applications to massively parallel processors, with two key distinctions:• FPGAs are far more different from uniprocessors than MPPs are from uniprocessors, and• the process of parallelizing code for MPPs, while challenging, is still better understood and supported than porting codes to FPGAs.Lawrence Snyder stated the three basic parameters for the MPP portability problem. 3 First, a parallel solution using P processors can improve the best sequential solution by a factor of P, at most. Second, HPC problems tend to have third-or fourth-order complexity, and so parallel computation, while essential, offers only modest benefits. Third, "the whole force of parallelism must be transferred to the problem, not converted to 'heat' of implementational overhead."Researchers have addressed the portability problem periodically over the past 30 years, with well-known approaches involving language design, optimizing compilers, emulation, software engineering tools and methods, and function and application libraries. It is generally agreed that compromises are required: Either restrict the variety of architectures or scope of application, or bound expectations of performance or ease of implementation.

Synchronization methods in parallel and distributed discrete-event simulation

“…Reconfigurable hardware, such as large Field Programmable Gate Arrays (FPGAs), exhibits the potential to deliver an order of magnitude speedup for compute-intensive kernels in scientific applications [162]. Such hardware is being integrated with general-purpose processors in next-generation reconfigurable supercomputing systems [163].…”

Implementing Machine Vision Systems Using FPGAs

“…• The optimal processing mode in hardware is usually different from software [23]. Random memory access is efficient in software, especially with memory caching used by modern processors.…”

FPGA accelerator for floating-point matrix multiplication

“…Today's FPGAs are fast and large enough to allow hardware implementation of various algorithms that work faster compared to their software-only counterparts executing on generalpurpose microprocessors [1], [2], [3], [4], [5]. There is a plethora of research efforts regarding the use of FPGA accelerators to speed up critical parts of computationally-intensive programs.…”