Achieving Predictable Multicore Execution of Automotive Applications Using the LET Paradigm

Biondi, Alessandro; Natale, Marco Di

doi:10.1109/rtas.2018.00032

Cited by 59 publications

(41 citation statements)

References 15 publications

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“…Tice borrows its LET MoCC from Giotto , 18 which is gaining acceptance, particularly in the automotive industry, to facilitate the transition of embedded software from unicore to multicore processors 57 . The TCEL follow‐up paper that addresses the synthesis problem 58 inspires the kinds of temporal constraints that Tice can enforce, namely end‐to‐end delay and correlation constraints.…”

Section: Related Workmentioning

confidence: 99%

Tice: A real‐time language compilable using C++ compilers

2020

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Summary Model‐based development (MBD) holds the promise to capture potential timing problems in embedded software during the early phases of the development, securing the production of bug‐free embedded software. For most MBD approaches, the source code is just an intermediate artifact that can be generated automatically from the models. This assumption clashes with an undeniable fact: a large share of the commercial embedded software exploits existing libraries or is developed using C/C++ natively. A way to reconcile the ambitions of MBD with the use of a programming language is by offering new language constructs and an innovative compilation tool‐chain that prevents model error and timing problems “by construction.” However, the persistent popularity of C/C++ among embedded programmers and the limited availability of tools have severely limited the uptake of alternative programming languages for embedded software. Therefore, we propose an original route. Our language proposal, named Tice, has been shaped as a C++ active library. Tice retains full compatibility with existing C++ code, which can be integrated easily into new Tice‐based projects. The enforcement of Tice syntax and semantics can be made by a standard C++ compiler, forgoing the need for new tools. In this article, we describe Tice's syntax, semantics, and model of computation and communication. We demonstrate Tice's practical applicability on an industrial scale use‐case and give ample evidence for Tice's efficient compilation using off‐the‐shelf C++ compilers. Finally, we show Tice's code generation process.

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Section: Related Workmentioning

confidence: 99%

Tice: A real‐time language compilable using C++ compilers

2020

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“…A first class of approaches aims at limiting the amount of contention in a system or avoiding contention altogether. Some approaches [41], [40], [6], [11], [13] rely on an execution model where task execution is split into memory and computation phases, where accesses to shared resources (i.e., memory system) exclusively happen during memory phases. Tasks are, therefore, scheduled in a way to avoid overlapping of memory phases.…”

Section: Related Workmentioning

confidence: 99%

“…Several studies [41], [40], [6], [11], [13] assume an application semantics that clearly separates phases dedicated to data exchange (E) (usually from/to a local on-chip memory) from phases devoted to pure computation (C). Phases are usually exploited to devise scheduling solutions [40], [6], [11], [13] aiming at conflict avoidance, but they also naturally constrain the possible task overlappings and, hence, access pairing. While we are not interested in imposing restrictions, we are interested in evaluating the potential WCD reduction that can be achieved under a favorable -and more constrictive -computation model and scenario, where additional details are available.…”

Section: Supporting Multiple Execution Phasesmentioning

confidence: 99%

“…Several approaches have been proposed for the characterization of inter-core interference on hardware resources. Some of them aim at exploiting hardware or software level mechanisms to control [29], [50], [38] or even to entirely avoid [41], [40], [6], [11], [13] the effects of contention. While provably effective, these approaches typically build on some assumptions on hardware, RTOS support, and/or application characteristics (e.g., phased execution [41]) that cannot always be guaranteed to hold in practice, especially in COTS platforms.…”

Section: Introductionmentioning

confidence: 99%

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Accurate ILP-Based Contention Modeling on Statically Scheduled Multicore Systems

Palomo

Mezzetti

Abella

et al. 2019

2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Commercially available Off The Shelf (COTS) multicores have been assessed as the baseline computing platform even in the most conservative real-time domains. Multicore contention arising on shared hardware resources, with its circular dependence with scheduling, is among the most challenging issues that require urgent attention before multicores can be fully embraced for real-time computing. In the context of static scheduling, still the most used scheduling approach in realtime industries, we propose an ILP formulation for computing the worst-case contention delay suffered by a task due to interference on a shared bus. Our model provides accurate contention delay bounds that avoid unnecessary over-accounting of conflicts between bus requests, by considering contention effects at system-level (i.e., across tasks) rather than at task-level only. This allows precisely capturing the interdependence between timing interference of conflicting requests, issued in parallel by other cores (tasks), and the identification of the particular set of tasks co-running on those cores. We assess our technique both analytically and empirically on a real COTS multicore platform. We show, via extensive evaluation, that jointly accounting for worst-case task overlapping and request distribution scenarios always provides tighter contention bounds when compared to state-of-the-art solutions.

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“…If these variables are placed alongside with the data of the tasks, additional interferences must be accounted because of the parallel execution of the controller. To reduce this additional negative effect, the status vectors should be placed in: i) a separate memory accessed by a separate bus, when the platform provides such a feature, or ii) the local memory of each core and accessed through remote writes [11].…”

Section: Response Time Analysismentioning

confidence: 99%

Timely Fine-Grained Interference-Sensitive Run-Time Adaptation of Time-Triggered Schedules

Skalistis

Kritikakou

2019

2019 IEEE Real-Time Systems Symposium (RTSS)

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In time-critical systems, run-time adaptation is required to improve the performance of time-triggered execution, derived based on Worst-Case Execution Time (WCET) of tasks. By improving performance, the systems can provide higher Quality-of-Service, in safety-critical systems, or execute other best-effort applications, in mixed-critical systems. To achieve this goal, we propose a parallel interference-sensitive run-time adaptation mechanism that enables a fine-grained synchronisation among cores. Since the run-time adaptation of offline solutions can potentially violate the timing guarantees, we present the Response-Time Analysis (RTA) of the proposed mechanism showing that the system execution is free of timing-anomalies. The RTA takes into account the timing behavior of the proposed mechanism and its associated WCET. To support our contribution, we evaluate the behavior and the scalability of the proposed approach for different application types and execution configurations on the 8-core Texas Instruments TMS320C6678 platform. The obtained results show significant performance improvement compared to state-of-the-art centralized approaches.

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Achieving Predictable Multicore Execution of Automotive Applications Using the LET Paradigm

Cited by 59 publications

References 15 publications

Tice: A real‐time language compilable using C++ compilers

Tice: A real‐time language compilable using C++ compilers

Accurate ILP-Based Contention Modeling on Statically Scheduled Multicore Systems

Timely Fine-Grained Interference-Sensitive Run-Time Adaptation of Time-Triggered Schedules

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