2018
DOI: 10.1088/1361-6528/aaf1e5
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Achieving short high-quality gate-all-around structures for horizontal nanowire field-effect transistors

Abstract: We introduce a fabrication method for gate-all-around nanowire field-effect transistors. Single nanowires were aligned perpendicular to underlying bottom gates using a resist-trench alignment technique. Top gates were then defined aligned to the bottom gates to form gate-all-around structures. This approach overcomes significant limitations in minimal obtainable gate length and gate-length control in previous horizontal wrap-gated nanowire transistors that arise because the gate is defined by wet etching. In t… Show more

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Cited by 17 publications
(15 citation statements)
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“…The HfO 2 layer is not required but included as an etch-stop layer for cases where an oxide-etch is needed in later processing. 49,82 We protect the front-side with hard-baked photoresist, etch the back-side oxide to completion in buffered Electrical measurements: Electrical measurements were performed with devices mounted on an Oxford Instruments Heliox VL 3 He system loaded into a liquid helium dewar (Wessington CH-120). This system has a small 2 T superconducting solenoid integrated into the sample-space vacuum can.…”
Section: Discussionmentioning
confidence: 99%
See 1 more Smart Citation
“…The HfO 2 layer is not required but included as an etch-stop layer for cases where an oxide-etch is needed in later processing. 49,82 We protect the front-side with hard-baked photoresist, etch the back-side oxide to completion in buffered Electrical measurements: Electrical measurements were performed with devices mounted on an Oxford Instruments Heliox VL 3 He system loaded into a liquid helium dewar (Wessington CH-120). This system has a small 2 T superconducting solenoid integrated into the sample-space vacuum can.…”
Section: Discussionmentioning
confidence: 99%
“…Another solution for thicker nanofins would be to use a global back-gate to lower the density independently of other patterned local top-or back-gates. 81,82 Regarding the gate insulator, one possibility is to avoid ALD-deposited oxides and opt for alternative insulators, e.g., parylene. 83 We make one final comment regarding the data in Figs.…”
Section: Electrical Characterisation Of Hall-configuration Nanofin De...mentioning
confidence: 99%
“…[2] The synthetic approaches control their composition, size and electronic structure (energy levels, density of states within the bands and in the bandgap) and the charge-carrier transport. For this reason, nanowires and nanotubes are particularly attractive in nanoelectronics and optoelectronics as functional interconnects, building blocks of nanotransistors, [4,5] light-emitting diodes [6] or detectors of radiation. Its great importance stems from the fact that it is a noncontact method and, owing to its high frequency and broadband character, it is capable of characterizing charge transport properties within individual nano-objects but also among them.…”
mentioning
confidence: 99%
“…So far, the highest mobility of 200 cm 2 /V.s has been recently achieved from amorphous zinc oxynitride thin film [14]. Gluschke et al [15] recently demonstrated a new fabrication method for high-quality gate-allaround TFT structure with independent top and bottom gate lengths. This approach overcomes significant limitations that exist in the wrap-gated NR transistors and the subthreshold swings achieved by this method as low as 38 mV/dec at 77 K for a 150 nm gate length TFT.…”
Section: Emerging Device Applications Of Nanorodsmentioning
confidence: 99%