Activation of silicon wafer by excimer laser

Paetzel, Rainer; Brune, J.; Simon, Frank; Herbst, Ludolf; Machida, Masashi; Shida, Junichi

doi:10.1109/rtp.2010.5623789

Cited by 6 publications

(5 citation statements)

References 7 publications

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“…The above spoken Raman characteristics indicated the presence of compressive strain in the film [51], supporting the formation of Q-carbon [31]. The chemical and surface changes induced by excimer laser wavelength were also observed for silicon and semiconductors [52,53] or silicon carbide [54][55][56]. The discussion on the correlation of surface morphology (e.g., SEM and AFM images) and I D /I G ratio changes were included in the papers [57,58].…”

Section: Raman Spectroscopymentioning

confidence: 78%

Carbon Transformation Induced by High Energy Excimer Treatment

et al. 2022

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The main aim of this study was to describe the treatment of carbon sheet with a high-energy excimer laser. The excimer modification changed the surface chemistry and morphology of carbon. The appearance of specific carbon forms and modifications have been detected due to exposure to laser beam fluencies up to 8 J.cm−2. High fluence optics was used for dramatic changes in the carbon layer with the possibility of Q-carbon formation; a specific amorphous carbon phase was detected with Raman spectroscopy. The changes in morphology were determined with atomic force microscopy and confirmed with scanning electron microscopy, where the partial formation of the Q-carbon phase was detected. Energy dispersive spectroscopy (EDS) was applied for a detailed study of surface chemistry. The particular shift of functional groups induced on laser-treated areas was determined by X-ray photoelectron spectroscopy. For the first time, high-dose laser exposure successfully induced a specific amorphous carbon phase.

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Section: Raman Spectroscopymentioning

confidence: 78%

Carbon Transformation Induced by High Energy Excimer Treatment

et al. 2022

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“…For the dopant activation of the S/D in the TFT, excimer laser annealing (ELA) instead of RTA was applied. Because a penetration depth of an excimer laser is 6 nm and the first ILD is a good thermal insulator, thermal damage to the underlying TTSs and metal interconnections is preventable . Then, another TEOS of 300 nm was deposited as a second interlayer dielectric (2nd ILD) to avoid electrical short between upper metal interconnections and the TFTs.…”

Section: Resultsmentioning

confidence: 99%

“…Because a penetration depth of an excimer laser is 6 nm and the first ILD is a good thermal insulator, thermal damage to the underlying TTSs and metal interconnections is preventable. 18 Then, another TEOS of 300 nm was deposited as a second interlayer dielectric (2nd ILD) to avoid electrical short between upper metal interconnections and the TFTs. Then, a second level of holes and metal interconnections was followed to interconnect underlaying TTSs and superjacent TFTs.…”

Section: ■ Results and Discussionmentioning

confidence: 99%

Vertically Integrated CMOS Ternary Logic Device with Low Static Power Consumption and High Packing Density

Han,

Lee,

Kim

et al. 2023

ACS Appl. Mater. Interfaces

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A ternary logic system to realize the simplest multivalued logic architecture can enhance energy efficiency compared to a binary logic system by reducing the number of transistors and interconnections. For the ternary logic system, a ternary logic device to harness three stable states is needed. In this study, a vertically integrated complementary metal−oxide−semiconductor ternary logic device is demonstrated by monolithically integrating a thin-film transistor (TFT) over a transistor-based threshold switch (TTS). Because the TFT and the TTS have their own source (S), drain (D), and gate (G), there are physically six electrodes. But the hybrid ternary logic device of the TFT over the TTS has only four electrodes: S, D, G TFT , and G TTS like a single MOSFET. It is because the D of the underlying TTS is electrically tied with the S of the superjacent TFT. By combining an on-and off-state of the TFT and the TTS, ternary logic values of low current ("0"-state), middle current ("1"-state), and high current ("2"-state) are realized. Particularly, static power consumption at the "1"-state is decreased by employing the TTS with low off-state leakage current compared to previously reported other ternary logic devices. In addition, a footprint of the ternary logic device with the vertically overlaying structure that has a framework of "one over the other" can be lowered by roughly twice compared to that with the laterally deployed structure that has an organization of "one alongside the other".

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“…Compared to the poly‐Si channel thickness of 50 nm and poly‐Si gate thickness of 100 nm and the first ILD layer with a thickness of 300 nm, the penetration depth of ≈6 nm stemming from its short wavelength is shallow. [ 38 ] Thus, the heat induced by ELA cannot be transferred to other areas apart from the exposed S/D of the 1TFT‐synapse.…”

Section: Resultsmentioning

confidence: 99%

3D Neuromorphic Hardware with Single Thin‐Film Transistor Synapses Over Single Thin‐Body Transistor Neurons by Monolithic Vertical Integration

Han,

Lee,

Kim

et al. 2023

Advanced Science

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Neuromorphic hardware with a spiking neural network (SNN) can significantly enhance the energy efficiency for artificial intelligence (AI) functions owing to its event‐driven and spatiotemporally sparse operations. However, an artificial neuron and synapse based on complex complementary metal‐oxide‐semiconductor (CMOS) circuits limit the scalability and energy efficiency of neuromorphic hardware. In this work, a neuromorphic module is demonstrated composed of synapses over neurons realized by monolithic vertical integration. The synapse at top is a single thin‐film transistor (1TFT‐synapse) made of poly‐crystalline silicon film and the neuron at bottom is another single transistor (1T‐neuron) made of single‐crystalline silicon. Excimer laser annealing (ELA) is applied to activate dopants for the 1TFT‐synapse at the top and rapid thermal annealing (RTA) is applied to do so for the 1T‐neuron at the bottom. Internal electro‐thermal annealing (ETA) via the generation of Joule heat is also used to enhance the endurance of the 1TFT‐synapse without transferring heat to the 1T‐neuron at the bottom. As neuromorphic vision sensing, classification of American Sign Language (ASL) is conducted with the fabricated neuromorphic module. Its classification accuracy on ASL is ≈92.3% even after 204 800 update pulses.

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Activation of silicon wafer by excimer laser

Cited by 6 publications

References 7 publications

Carbon Transformation Induced by High Energy Excimer Treatment

Carbon Transformation Induced by High Energy Excimer Treatment

Vertically Integrated CMOS Ternary Logic Device with Low Static Power Consumption and High Packing Density

3D Neuromorphic Hardware with Single Thin‐Film Transistor Synapses Over Single Thin‐Body Transistor Neurons by Monolithic Vertical Integration

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