Active Guardband Management in Power7+ to Save Energy and Maintain Reliability

Lefurgy, Charles; Drake, Alan J.; Floyd, Michael S.; Allen-Ware, Malcolm; Brock, Bishop; Tierno, J.; Carter, J. B.; Berry, Robert W.

doi:10.1109/mm.2013.52

Cited by 54 publications

(22 citation statements)

References 4 publications

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“…REACTIVE CLOCKS WITH VARIABILITY-TRACKING JITTER Various techniques have been proposed to mitigate the impact of variability. Parametric binning [9] performs at-speed testing to eliminate margins associated with global static variability, while Adaptive Clocks (AClk) attack dynamic variability by modifying the clock frequency when sensing changes in the operating conditions [7], [10], [11]. Unfortunately, the aforementioned techniques cannot get rid of some guardband margins because they cannot handle fast variability efficiently-more details are provided in Section VIII.…”

Section: Variability Margins and Static Timing Analysismentioning

confidence: 99%

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Reactive clocks with variability-tracking jitter

Cortadella

Lavagno

López

et al. 2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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Abstract-The growing variability in nanoelectronic devices, due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging), requires increasing design guardbands, forcing circuits to work with conservative clock frequencies. Various schemes for clock generation based on ring oscillators and adaptive clocks have been proposed with the goal to mitigate the power and performance losses attributable to variability. However, there has been no systematic analysis to quantify the benefits of such schemes and no signoff method has been proposed for timing correctness. This paper presents and analyzes a Reactive Clocking scheme with Variability-Tracking Jitter (RClk) that uses variability as an opportunity to reduce power by continuously adjusting the clock frequency to the varying environmental conditions, and thus, reduces guardband margins significantly. Power can be reduced between 20% and 40% at iso-performance and performance can be boosted by similar amounts at iso-power. Additionally, energy savings can be translated to substantial advantages in terms of reliability and thermal management. More importantly, the technology can be adopted with minimal modifications to conventional EDA flows.

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Section: Variability Margins and Static Timing Analysismentioning

confidence: 99%

“…After detection, different reaction schemes are proposed. One possible reaction is to quickly modify the clock frequency generated by a DLL [10], [11]. Another possibility is to stop the clock during the droop until the voltage returns to a stable level [22].…”

Section: Related Workmentioning

confidence: 99%

Reactive clocks with variability-tracking jitter

Cortadella

Lavagno

López

et al. 2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

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“…Several studies have shown that CPM can effectively provide timing margin information at every clock cycle for speedy response with only a slight increase in design complexity and area [9][10][11][12]. We transform this delay information into the threshold voltage of each core.…”

Section: Tunable Ntc Architecturementioning

confidence: 99%

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

Li¹,

Kim²,

Heo³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Near-threshold computing (NTC) is now regarded as a promising candidate for innovative power reduction, which cannot be achieved with conventional super-threshold computing (STC). However, performance degradation and vulnerability to process variation in the NTC regime are the primary concerns. In this paper, we propose a voltage-and frequency-tuning methodology for mitigating the process-variation-induced problems in NTC-based manycore architectures. To implement the proposed methodology, we build up multiplevoltage multiple-frequency (MVMF) islands and apply a voltage-frequency tuning algorithm based on the critical-path monitoring technique to reduce the effects of process variation and maximize energy efficiency in the post-silicon stage. Experimental results show that the proposed methodology reduces overall power consumption by 8.2-20.0%, compared to existing methods in variation-sensitive NTC environments.

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“…When emergencies are detected, recovery mechanisms will be applied to roll back the architectural state, such as the registers and memory state, to a guaranteed-correct state. Because such rollback mechanisms can be prohibitively expensive, researchers have also developed voltage emergency predictors [6][7][8][9], based on current/voltage profiles, microarchitectural signatures etc., to identify impending emergencies and prevent their occurrence by throttling mechanisms. These throttling mechanisms try to reduce current variations by either reducing the processor's clock rate [10], or activating idle functional units when there is a sudden reduction in current draw [6], or controlling instruction issue and current change in the pipelines [11,12].…”

Section: Introductionmentioning

confidence: 99%

“…For example, in Intel processors, error detection circuits EDS and TRC [2] are used to achieve delay fault detection; in IBM POWER7 server [7], a sensor-based throttling approach called Critical Path Monitoring (CPM) has been implemented to measure the available timing margin in real time.…”

Section: Introductionmentioning

confidence: 99%

A statistical methodology for noise sensor placement and full-chip voltage map generation

Liu

Sun

Zhou

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Noise margin violation, also known as voltage emergency induced by continuously reducing noise margin and increasing magnitude of current swings, is becoming a severe threat to the correct execution of applications in processors. Noise sensors can be placed in the non-function area of processors to detect such emergencies by monitoring runtime voltage fluctuations. In this work, we aim to accurately predict the voltage droops using a small set of sensors. We achieve our goal in two steps: We first propose a methodology via group lasso approach to select the optimal set of noise sensors, then build a practical model via ordinary least-squares fitting approach to predict the voltage in the function area of the chip, using the selected sensors in non-function area. Experiment results show that when compared to the full-chip voltage transient simulation, the prediction error of our model is much less than 0.01, and compared to prior work, our approach can achieve better error rates of voltage emergency detection (less than half).

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Active Guardband Management in Power7+ to Save Energy and Maintain Reliability

Cited by 54 publications

References 4 publications

Reactive clocks with variability-tracking jitter

Reactive clocks with variability-tracking jitter

Voltage and Frequency Tuning Methodology for Near-Threshold Manycore Computing using Critical Path Delay Variation

A statistical methodology for noise sensor placement and full-chip voltage map generation

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