Active management of timing guardband to save energy in POWER7

Abstract

Microprocessor voltage levels include substantial margin to deal with process variation, system power supply variation, workload induced thermal and voltage variation, aging, random uncertainty, and test inaccuracy. This margin allows the microprocessor to operate correctly during worst-case conditions, but during typical conditions it is larger than necessary and wastes energy. We present a mechanism that reduces excess voltage margin by (1) introducing a critical path monitor (CPM) circuit that measures available timing margin in real-time, (2) coupling the CPM output to the clock generation circuit to adjust clock frequency within cycles in response to excess or inadequate timing margin, and (3) adjusting the processor voltage level periodically in firmware to achieve a specified average clock frequency target. We implemented this mechanism in a prototype IBM POWER7 server. During better-than-worst case conditions our guardband management mechanism reduces the average voltage setting 137-152 mV below nominal, resulting in average processor power reduction of 24% with no performance loss while running industry-standard benchmarks.

Accurate Fine-Grained Processor Power Proxies

“…An interesting experiment would be to test the power proxy's accuracy when voltage and frequency pairs are not fixed. Recently, Lefurgy et al [12] proposed a method of safely undervolting a microprocessor while maintaining the same frequency. Voltage is dynamically selected to maintain a preset guardband level as chip activity changes, resulting in reduced chip power without performance loss.…”

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

“…EVAL is targeted at timing errors and improving performance in the face of process variation. More recently, Lefurgy et al [15] developed a solution for lowering voltage margins in IBM Power 7 processors. Their solution uses critical path monitors built into the chip to detect when margins are about to be exceeded.…”

“…Additional latches running on a delayed clock are used on the vulnerable paths to detect and recover from these errors. More recent work by Lefurgy et al [15] uses on-chip critical path monitors to detect when a processor is approaching its timing margin as a result of voltage speculation. When that occurs, a control system slows the processor frequency to avoid a timing violation.…”

Performance boosting under reliability and power constraints

“…The work that comes closest in terms of a hardware implementation is the work by Lefurgy et al [11], which addressed actively monitoring and managing the voltage guardband based on the use of a critical-path monitor (CPM). The CPM monitors the critical pathways in the chip and increases the voltage guardband if the CPM detects potential errors.…”