The modular multilevel converter (MMC) has become very attractive for high-and medium-voltage applications, generating excellent waveforms at very high efficiencies. One of the main challenges is the appropriate selection of inserted submodules (SMs), commonly done by capacitor voltage balancing algorithms. However, the semiconductor stress can only be balanced up to a certain degree by conventional algorithms, since the stress is not directly monitored. An uneven stress distribution between the SMs does not only result in different lifetime expectations, but also in increased maximum temperatures, for which each SM needs to be designed. With the goal of more effective utilization of chip area, a new balancing approach is introduced for monitoring and balancing not only the capacitor voltages but also the average power losses in each SM. In this way, the MMC current capability is significantly increased only by software without deteriorating the system performance and efficiency.