AD-LRU: An efficient buffer replacement algorithm for flash-based databases

Jin, Peiquan; Ou, Yun; Härder, Theo; Li, Zhi

doi:10.1016/j.datak.2011.09.007

Cited by 81 publications

(37 citation statements)

References 10 publications

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“…But based on PCM main memory, LLC management problem is similar to DRAM cache management problem for flash SSD storage [63][64][65][66][67][68]. Due to PCM's poor write performance, to improve the overall performance, the cache management policy should consider not only the hit ratio but a lso reducing write-backs from LLC to PCM.…”

Section: Pure Pcm Main Memorymentioning

confidence: 99%

A Survey on Phase Change Memory-Aware Cache Management

Chen

Jin

Yue

2016

IJMUE

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Section: Pure Pcm Main Memorymentioning

confidence: 99%

A Survey on Phase Change Memory-Aware Cache Management

Chen

Jin

Yue

2016

IJMUE

Self Cite

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“…AD-LRU [7] tries to solve the problem of CCF-LRU by adjusting the size of cold list. It divides the buffer into cold When there are no cold clean pages, if the size of cold list is more than min lc, the cold dirty pages from the cold list will be selected as victims.…”

Section: Related Workmentioning

confidence: 99%

LAB-LRU: A Life-Aware Buffer Management Algorithm for NAND Flash Memory

Wang

Chen

Hao

2016

IEICE Trans. Inf. & Syst.

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SUMMARY NAND flash memory has been widely used in storage systems. Aiming to design an efficient buffer policy for NAND flash memory, a life-aware buffer management algorithm named LAB-LRU is proposed, which manages the buffer by three LRU lists. A life value is defined for every page and the active pages with higher life value can stay longer in the buffer. The definition of life value considers the effect of access frequency, recency and the cost of flash read and write operations. A series of tracedriven simulations are carried out and the experimental results show that the proposed LAB-LRU algorithm outperforms the previous best-known algorithms significantly in terms of the buffer hit ratio, the numbers of flash write and read operations and overall runtime. key words: NAND flash memory, storage system, buffer management algorithm, life value

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“…Cold-Clean-First LRU (CCFLRU) [12] policy enhanced CFLRU and LRU-WSR methods by differentiating clean pages into cold and hot ones, and evicting cold clean pages first and delaying the eviction of hot clean pages. AD-LRU [21] sets the lowest limit for the size of the cold list. FOR [22] combines inter-operation distance and operation recency to determine the hotness of an operation, which are used to calculate the weight of each page to evict.…”

Section: Related Workmentioning

confidence: 99%

“…Recently a few cache management techniques [18]- [20] have been proposed to mitigate the write overhead of PCM, but most of them are performed on PCM itself, without optimizing the write traffic sent from LLC. In addition, there are some buffer management policies [12], [21], [22] that can reduce the writebacks to NAND Flash, but they fall short in efficiency and are difficult to implement on chip. To • The base ARW policies, which consider the asymmetric costs of read and write operations by setting different evicting priorities, are proposed to minimize the write traffic.…”

Section: Introductionmentioning

confidence: 99%

ARW: Efficient Replacement Policies for Phase Change Memory and NAND Flash

Zhang¹,

Duan²,

Yang³

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYThe write operations on emerging Non-Volatile Memory (NVM), such as NAND Flash and Phase Change Memory (PCM), usually incur high access latency, and are required to be optimized. In this paper, we propose Asymmetric Read-Write (ARW) policies to minimize the write traffic sent to NVM. ARW policies exploit the asymmetry costs of read and write operations, and make adjustments on the insertion policy and hit-promotion policy of the replacement algorithm. ARW can reduce the write traffic to NVM by preventing dirty data blocks from frequent evictions. We evaluate ARW policies on systems with PCM as main memory and NAND Flash as disk. Simulation results on an 8-core multicore show that ARW adopted on the last-level cache (LLC) can reduce write traffic by more than 15% on average compared to LRU baseline. When used on both LLC and DRAM cache, ARW policies achieve an impressive reduction of 40% in write traffic without system performance degradation. When employed on the on-disk buffer of the Solid State Drive (SSD), ARW demonstrates significant reductions in both write traffic and overall access latency. Moreover, ARW policies are lightweight, easy to implement, and incur negligible storage and runtime overhead.

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AD-LRU: An efficient buffer replacement algorithm for flash-based databases

Cited by 81 publications

References 10 publications

A Survey on Phase Change Memory-Aware Cache Management

A Survey on Phase Change Memory-Aware Cache Management

LAB-LRU: A Life-Aware Buffer Management Algorithm for NAND Flash Memory

ARW: Efficient Replacement Policies for Phase Change Memory and NAND Flash

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