Adaptable performance MOS current mode logic for use in a 3GHz programmable frequency divider

Houlgate, Mark; Olszewski, D.J.; Abdelhalim, Karim; MacEachern, L.

doi:10.1109/mwscas.2003.1562534

Cited by 3 publications

(1 citation statement)

References 3 publications

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“…The voltage swing values should be more than 1.4 V dssat , where V dssat is the saturation drain-source voltage of the differential transistor pair for functionality to remain intact [20]. It may further be noted that the proposed MCML gates can maintain constant voltage swing against process variation by modifying their load section by using adaptive bias controller as suggested in [21,22].…”

Section: Vlsi Designmentioning

confidence: 99%

New Proposal for MCML Based Three-Input Logic Implementation

2016

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This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included.

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Section: Vlsi Designmentioning

confidence: 99%

New Proposal for MCML Based Three-Input Logic Implementation

2016

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1V High Speed E-TSPC 2/3 Prescalers

Lawang

Tudsorn

Tooprakai

2019

2019 5th International Conference on Engineering, Applied Sciences and Technology (ICEAST)

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Wide-division-range high-speed fully programmable frequency divider

Sleiman

Atallah

Rodriguez

et al. 2008

2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference

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This paper presents the design and implementation of an all-programmable frequency divider with an ultra-wide division range for use in Phase-Locked Loops. The proposed divider uses a fully modular architecture and dynamic logic -implemented in TSMC 0.18μm -and can divide input frequencies up to 7.55GHz by any ratio between 8 and 255 while consuming 11mW from a 1.8V power supply. The divider compares very favorably to other implementations reported in literature in terms of division range and frequency of operation.

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Adaptable performance MOS current mode logic for use in a 3GHz programmable frequency divider

Cited by 3 publications

References 3 publications

New Proposal for MCML Based Three-Input Logic Implementation

New Proposal for MCML Based Three-Input Logic Implementation

1V High Speed E-TSPC 2/3 Prescalers

Wide-division-range high-speed fully programmable frequency divider

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