Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories

Nakamura, Toshiki; Deguchi, Yoshiaki; Takeuchi, Ken

doi:10.1109/jssc.2018.2884949

Cited by 22 publications

(6 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In Figure 9 a,b, we compare RBER and frame error rate (FER) using ANN-LDPC [ 11 ], the proposed method and the original method without the neural network versus data retention time at

. We can observe that the proposed ANNAEC significantly reduces the RBER in comparison with the ANN-LDPC and original method.…”

Section: Experiments Resultsmentioning

confidence: 99%

“…The key idea of the neural network is to learn an optimal network model from the massive training data, instead of using a definitive algorithm that is derived from a pre-defined model [ 9 ]. A pioneering work is reported in [ 10 , 11 ], which utilizes an artificial neural network to predict the threshold voltage distribution of NAND flash memory. In the pretesting, the above method assumes that the prior information of the retention time is informed in advance.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Xiong

et al. 2021

Micromachines

View full text Add to dashboard Cite

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

show abstract

“…In Figure 9 a,b, we compare RBER and frame error rate (FER) using ANN-LDPC [ 11 ], the proposed method and the original method without the neural network versus data retention time at

. We can observe that the proposed ANNAEC significantly reduces the RBER in comparison with the ANN-LDPC and original method.…”

Section: Experiments Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Xiong

et al. 2021

Micromachines

View full text Add to dashboard Cite

show abstract

“…A similar approach, although oriented to 3D NAND flash architectures was proposed in [23], where, for the first time, the authors introduced the use of the gamma-Poisson distribution for error modeling, and in [24], where a generalized Pareto distribution was used to model real disturb errors. Other interesting solutions have relied on machine learning algorithms for memory lifetime classification and prediction [13,15,16] and on deep neural networks [25][26][27]. However, some of the developed models require a huge characterization dataset and significant computing power to run the model training process or the creation of a dedicated computational framework based on neural networks to optimize the device characteristics, such as the case discussed in [28] though for a different technology.…”

Section: Introductionmentioning

confidence: 99%

Modeling 3D NAND Flash with Nonparametric Inference on Regression Coefficients for Reliable Solid-State Storage

Borghesi,

Zambelli,

Micheloni

et al. 2023

Future Internet

View full text Add to dashboard Cite

Solid-state drives represent the preferred backbone storage solution thanks to their low latency and high throughput capabilities compared to mechanical hard disk drives. The performance of a drive is intertwined with the reliability of the memories; hence, modeling their reliability is an important task to be performed as a support for storage system designers. In the literature, storage developers devise dedicated parametric statistical approaches to model the evolution of the memory’s error distribution through well-known statistical frameworks. Some of these well-founded reliability models have a deep connection with the 3D NAND flash technology. In fact, the more precise and accurate the model, the less the probability of incurring storage performance slowdowns. In this work, to avoid some limitations of the parametric methods, a non-parametric approach to test the model goodness-of-fit based on combined permutation tests is carried out. The results show that the electrical characterization of different memory blocks and pages tested provides an FBC feature that can be well-modeled using a multiple regression analysis.

show abstract

“…The shrinking of technological dimension and the increasing of storage density increase error codes of NAND Flash Memory increasingly, accompanied with sharp reduction of P/E cycles. Abundant Channel Coding Scheme have been developed so far to improve reliability of NAND Flash Memory [1][2][3][4][5]. LDPC is the most popular one.…”

Section: Introductionmentioning

confidence: 99%

A Novel Channel Coding Scheme by Concatenating LDPC with BCH for NAND Flash Memory

Jiang

et al. 2022

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

Insuring data reliability on NAND Flash Memory is an important research issue. As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays NAND Flash memory, Low Density Parity Check (LDPC) codes are recently proposed due to their outstanding error correcting capability. In this paper, a novel Channel Coding Scheme concatenated LDPC with BCH NAND Flash Memory is proposed. Firstly a particular LDPC code with low error floor is constructed and BCH codes are used to generate soft information for LDPC codes. Simulation showed that the proposed Channel Coding Scheme obtains the benefit of both overcoming difficulties of soft information generation and the compatiblity with existing BCH code. With the low error floor of constructed LDPC codes, the proposed Channel Coding Scheme can increase P/E cycles of NAND flash memory more significantly comparing the BCH code.

show abstract

Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories

Cited by 22 publications

References 12 publications

Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Modeling 3D NAND Flash with Nonparametric Inference on Regression Coefficients for Reliable Solid-State Storage

A Novel Channel Coding Scheme by Concatenating LDPC with BCH for NAND Flash Memory

Contact Info

Product

Resources

About