Adaptive Cache Structures

Tradowsky, Carsten; Cordero, Enrique; Orsinger, Christoph; Vesper, Malte; Becker, J.

doi:10.1007/978-3-319-30695-7_7

Cited by 3 publications

(2 citation statements)

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“…The general structure of an adaptive cache is one composed of a number of small independent memory blocks that can be reconfigured into different logical organizations to support (i) multiple associativities, (ii) flexible datablock widths, and (iii) adjustable number of cache entries [24]. Figure 1 depicts how the logical organization of a set of uniform memory blocks is reorganized to provide the functionality of different cache configurations.…”

Section: Adaptive-reconfigurable Cache Securitymentioning

confidence: 99%

“…As highlighted in Figs. 20,21,22,23,24, and 25, the effect of reconfiguration is virtually non-existent after the prime phase is completed. However, this may not be completely accurate, since the results are based on the assumption that the combined effect of reconfiguration and flushing is the sum of the individual effects, which has not been fully validated.…”

Section: Estimating the Effect Of Cache Flushingmentioning

confidence: 99%

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Adaptive caches as a defense mechanism against cache side-channel attacks

Bandara

Kinsy

2020

J Cryptogr Eng

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Side-channel attacks exploit architectural features of computing systems and algorithmic properties of applications executing on these systems to steal sensitive information. Cache side-channel attacks are more powerful and practical compared to other classes of side-channel attacks due to several factors, such as the ability to be mounted without physical access to the system. Some secure cache architectures have been proposed to counter side-channel attacks. However, they all incur significant performance overheads. This work explores the viability of using adaptive caches, which are conventionally used as a performance-oriented architectural feature, as a defense mechanism against cache side-channel attacks. We conduct an empirical analysis, starting from establishing a baseline for the attacker's ability to infer information regarding the memory accesses of the victim process when there is no active defense mechanism in place and the attacker is fully aware of all the cache parameters. Then, we analyze the effectiveness of the attack without complete knowledge of the cache configuration. Finally, based on the insight that the success of the attack is heavily dependent on knowledge of the cache configuration, we formulate a cache monitoring and user-defined events detection methodology, implement a generalized run-time cache reconfiguration technique, and observe their effect on successfully detecting and mitigating attacks on the cache subsystem. We observe that reconfiguring different cache parameters during a side-channel attack reduces the accuracy of the attack in detecting cache sets accessed by the victim by 44% on average, with a maximum of 90% reduction.Keywords Cache side-channel attack • Attack mitigation • Reconfigurable cache IntroductionMost modern processors use caches to overcome the "memory wall", which is the widening gap between processor speed and memory access speed. While being vital to the performance of a processor, they have also been the target of numerous side-channel attacks. Several recent sidechannel attacks exploit processor caches as the medium that transfers sensitive information from the victim to the B Sahan Bandara

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Section: Adaptive-reconfigurable Cache Securitymentioning

confidence: 99%