Adaptive Caches as a Defense Mechanism Against Cache Side-Channel Attacks

Bandara, Sahan; Kinsy, Michel A.

doi:10.1145/3338508.3359574

Cited by 6 publications

(4 citation statements)

References 17 publications

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“…This study emphasizes the additional functionality enabled by better visibility over data movement. Specifically, we demonstrate that täkō enables fine-grain monitoring of data for side-channel attacks [12,48,52,61,68,79,81,96,125,147].…”

Section: Detecting Side-channel Attacksmentioning

confidence: 97%

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täkō

Schwedock

Yoovidhya

Seibert

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Current systems hide data movement from software behind the load-store interface. Software's inability to observe and respond to data movement is the root cause of many inefficiencies, including the growing fraction of execution time and energy devoted to data movement itself. Recent specialized memory-hierarchy designs prove that large data-movement savings are possible. However, these designs require custom hardware, raising a large barrier to their practical adoption.This paper argues that the hardware-software interface is the problem, and custom hardware is often unnecessary with an expanded interface. The täkō architecture lets software observe data movement and interpose when desired. Specifically, caches in täkō can trigger software callbacks in response to misses, evictions, and writebacks. Callbacks run on reconfigurable dataflow engines placed near caches. Five case studies show that this interface covers a wide range of data-movement features and optimizations. Microarchitecturally, täkō is similar to recent near-data computing designs, adding ≈5% area to a baseline multicore. täkō improves performance by 1.4×-4.2×, similar to prior custom hardware designs, and comes within 1.8% of an idealized implementation. CCS CONCEPTS• Computer systems organization → Processors and memory architectures.

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Section: Detecting Side-channel Attacksmentioning

confidence: 97%

“…The Morph only implements one callback, onEviction, which simply interrupts the main thread whenever any cache line containing the AES tables is evicted. This interrupt lets the victim defend itself from attack [12,102,125]. Fig.…”

Section: Detecting Side-channel Attacksmentioning

confidence: 99%

täkō

Schwedock

Yoovidhya

Seibert

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

View full text Add to dashboard Cite

show abstract

“…These caches reconfigure cache parameters such as block size, number of sets, associativity, to optimize the performance. The empirical analysis of adaptive cache from a security standpoint against cache timing channel attacks was done in [84]. The hypothesis behind the analysis was that it is difficult for an attacker to create ES when the attacker is unaware of the underlying cache's configuration.…”

Section: Randomizing Cache Configurationmentioning

confidence: 99%

A Survey on Cache Timing Channel Attacks for Multicore Processors

Kaur

Das

2021

J Hardw Syst Secur

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Cache timing channel attacks has attained a lot of attention in the last decade. These attacks exploits the timing channel created by the significant time gap between cache and main memory accesses. It has been successfully implemented to leak the secret key of various cryptography algorithms. The latest advancements in cache attacks also exploit other microarchitectural components such as hardware prefetchers, branch predictor, and replacement engine, in addition to the cache memory. Detection of these attacks is a difficult task as the attacker process running in the processor must be detected before significant portion of the attack is complete. The major challenge for mitigation and defense mechanisms against these attacks is maintaining the system performance while disabling or avoiding these attacks. The overhead caused by detection, mitigation and defense mechanism must not be significant to system's performance. This paper discusses the research carried out in three aspects of cache security: cache timing channel attacks, detection techniques of these attacks, and defense mechanisms in details. KeywordsCache security • Cache timing channel attack • Side-channel attack • Covert channel attack • Detection techniques • Defense mechanisms

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“…This work expands upon our previous work [3]. The novel contributions include the description of a reference adaptive cache architecture and an attack detection mechanism, and analyzing the impact of cache flushing during cache reconfigurations on attack efficacy.…”

mentioning

confidence: 92%

Adaptive caches as a defense mechanism against cache side-channel attacks

Bandara

Kinsy

2020

J Cryptogr Eng

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Side-channel attacks exploit architectural features of computing systems and algorithmic properties of applications executing on these systems to steal sensitive information. Cache side-channel attacks are more powerful and practical compared to other classes of side-channel attacks due to several factors, such as the ability to be mounted without physical access to the system. Some secure cache architectures have been proposed to counter side-channel attacks. However, they all incur significant performance overheads. This work explores the viability of using adaptive caches, which are conventionally used as a performance-oriented architectural feature, as a defense mechanism against cache side-channel attacks. We conduct an empirical analysis, starting from establishing a baseline for the attacker's ability to infer information regarding the memory accesses of the victim process when there is no active defense mechanism in place and the attacker is fully aware of all the cache parameters. Then, we analyze the effectiveness of the attack without complete knowledge of the cache configuration. Finally, based on the insight that the success of the attack is heavily dependent on knowledge of the cache configuration, we formulate a cache monitoring and user-defined events detection methodology, implement a generalized run-time cache reconfiguration technique, and observe their effect on successfully detecting and mitigating attacks on the cache subsystem. We observe that reconfiguring different cache parameters during a side-channel attack reduces the accuracy of the attack in detecting cache sets accessed by the victim by 44% on average, with a maximum of 90% reduction.Keywords Cache side-channel attack • Attack mitigation • Reconfigurable cache IntroductionMost modern processors use caches to overcome the "memory wall", which is the widening gap between processor speed and memory access speed. While being vital to the performance of a processor, they have also been the target of numerous side-channel attacks. Several recent sidechannel attacks exploit processor caches as the medium that transfers sensitive information from the victim to the B Sahan Bandara

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Adaptive Caches as a Defense Mechanism Against Cache Side-Channel Attacks

Cited by 6 publications

References 17 publications

täkō

täkō

A Survey on Cache Timing Channel Attacks for Multicore Processors

Adaptive caches as a defense mechanism against cache side-channel attacks

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