Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder

Pastuszak, Grzegorz; Jakubowski, Mariusz

doi:10.1109/tcsvt.2012.2223791

Cited by 26 publications

(25 citation statements)

References 11 publications

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“…The algorithm can achieve results close to optimum even if the number of search points assigned to macroblocks is strongly limited and varies with time. The block diagram of the architecture supporting the adaptive computationally scalable motion estimation at the fine level [5] is depicted in Fig. 1.…”

Section: Design For Adaptive Motion Estimationmentioning

confidence: 99%

“…In the adaptive computationally scalable motion estimation system applied for the H.264/AVC [5], original and reference 898 blocks are read alternately from the same memories. This dataflow is inconvenient for high-resolution videos since the throughput is limited by memory access.…”

Section: New Architecturementioning

confidence: 99%

“…Except one design [5], architectures for the motion estimation consist of two parts assigned to the integer-pel and fractional-pel search [6][7][8][9][10][11][12][13][14][15]. This approach requires separate reference-pixel buffers for each part.…”

Section: Introductionmentioning

confidence: 99%

“…Some high-throughput interpolators have been proposed in the literature for H.264/AVC [5][6][7][8][9]. Their scheduling assumes two successive steps, one for the half-pel interpolation and another for the quarter-pel interpolation.…”

Section: Introductionmentioning

confidence: 99%

“…Similarly to the previous work dedicated to H.264/AVC [5], the modules can check one motion vector for an 898 block in each clock cycle. This feature makes the architecture suitable for different fast search algorithms as the order of motion vectors does not affect the architecture.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder

Pastuszak

Trochimiuk

2014

J Real-Time Image Proc

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This paper presents the architecture of the highthroughput compensator and the interpolator used in the motion estimation of the H.265/HEVC encoder. The architecture can process 898 blocks in each clock cycle. The design allows the random order of checked coding blocks and motion vectors. This feature makes the architecture suitable for different search algorithms. The interpolator embeds 64 multiplierless reconfigurable filter cores to support computations for different fractional-pel positions. Synthesis results show that the design can operate at 200 and 400 MHz when implemented in FPGA Arria II and TSMC 90 nm, respectively. The computational scalability enables the proposed architecture to trade the throughput for the compression efficiency. If 2160p@30fps video is encoded, the design clocked at 400 MHz can check about 100 motion vectors for 898 blocks.

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Section: Design For Adaptive Motion Estimationmentioning

confidence: 99%

Section: New Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder

Pastuszak

Trochimiuk

2014

J Real-Time Image Proc

Self Cite

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Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder

Pastuszak

Jakubowski

2015

J Sign Process Syst

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The adaptive computationally-scalable motion estimation algorithm and its hardware implementation allow the H.264/AVC encoder to achieve efficiencies close to optimal in real-time conditions. Particularly, the search algorithm achieves results close to optimum even if the number of search points assigned to macroblocks is strongly limited and varies with time. The architecture implementing the algorithm developed and reported previously takes at least 674 clock cycles to interpolate and load reference area, and the number cannot be decreased without decreasing the search range. This paper proposes some optimizations of the architecture to increase the maximal throughput achieved by the motion estimation system even four times. Firstly, the chroma interpolation follows the search process, whereas the luma interpolation precedes it. Secondly, the luma interpolator computes 128 instead of 64 samples per each clock cycle. Thirdly, the number of onchip memories keeping interpolated reference area is increased accordingly to 128. Fourthly, some modules previously working at the base frequency are redesigned to operate at the doubled clock. Since the on-chip memories do not store fractional-pel chroma samples, their joint size is reduced from 160.44 to 104.44 kB. Additional savings in the memory size are achieved by the sequential processing of two referencepicture areas for each macroblock. The architecture is verified in the real-time FPGA hardware encoder. Synthesis results show that the updated architecture can support 2160p@30fps encoding for 0.13 μm TSMC technology with a small increase in hardware resources and some losses in the compression efficiency. The efficiency is improved when processing smaller resolutions.

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High performance architecture for real-time HDTV broadcasting

Ismail

Elmedany

Al-Junaid

et al. 2014

J Real-Time Image Proc

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Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder

Cited by 26 publications

References 11 publications

Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder

Architecture design of the high-throughput compensator and interpolator for the H.265/HEVC encoder

Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder

High performance architecture for real-time HDTV broadcasting

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