Adaptive guardband scheduling to improve system-level efficiency of the POWER7+

Zu, Yazhou; Lefurgy, Charles; Leng, Jingwen; Halpern, Matthew; Floyd, Michael S.; Reddi, Vijay Janapa

doi:10.1145/2830772.2830824

Cited by 46 publications

(22 citation statements)

References 35 publications

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“…On non-resilient systems, errors must be avoided at all costs to guarantee correctness and to prevent escalation to a potentially catastrophic failure. Hence, manufacturers place margins on the voltage and clock frequency of their products, to ensure that even a slight fluctuation in the power input, or a single cosmic ray, does not alter any part of the computation [70]. Numerous studies have focused on inherent software resilience to hardware errors [43], or proposed software mitigation techniques to reduce or remove the effect of a fault.…”

Section: A Margins For Error-free Computationmentioning

confidence: 99%

“…While conventional commodity processors do not feature redundancy at the hardware level, manufacturers already sacrifice performance for reliability, by using costly safeguards to reduce error likelihoods [70], on both voltage and frequency margins, and to mitigate voltage spikes [32], [57]. Voltage margins are used to decrease the probability that a transistor exhibits errors when faced with an electrical fluctuation; undervolting can be used to claw back energy lost to these margins [51], [65].…”

Section: Introductionmentioning

confidence: 99%

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ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance

Ainsworth

Zoubritzky

Mycroft

et al. 2021

2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)

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Providing reliability is becoming a challenge for chip manufacturers, faced with simultaneously trying to improve miniaturization, performance and energy efficiency. This leads to very large margins on voltage and frequency, designed to avoid errors even in the worst case, along with significant hardware expenditure on eliminating voltage spikes and other forms of transient error, causing considerable inefficiency in power consumption and performance.We flip traditional ideas about reliability and performance around, by exploring the use of error resilience for power and performance gains. ParaMedic is a recent architecture that provides a solution for reliability with low overheads via automatic hardware error recovery. It works by splitting up checking onto many small cores in a heterogeneous multicore system with hardware logging support. However, its design is based on the idea that errors are exceptional. We transform ParaMedic into ParaDox, which shows high performance in both error-intensive and scarce-error scenarios, thus allowing correct execution even when undervolted and overclocked. Evaluation within error-intensive simulation environments confirms the error resilience of ParaDox and the low associated recovery cost. We estimate that compared to a non-resilient system with margins, ParaDox can reduce energy-delay product by 15% through undervolting, while completely recovering from any induced errors.

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Section: A Margins For Error-free Computationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance

Ainsworth

Zoubritzky

Mycroft

et al. 2021

2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)

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“…Recently, various power management techniques [3], [10]- [13] have been proposed to save power and improve the overall processor's performance at the system and architecture level. For example, [3] explores the benefits of fast DVFS at submicrosecond time scale using on-chip switching regulators.…”

Section: Related Workmentioning

confidence: 99%

“…For example, [3] explores the benefits of fast DVFS at submicrosecond time scale using on-chip switching regulators. And [13] proposes an adaptive guard-banding approach to dynamically adapt chip clock frequency and voltage based on timing-margin measurements at runtime. Different from these DVFS techniques which target the optimization of processor's power and performance, this work explores the energy reduction opportunity in the PDN which delivers energy to the processor.…”

Section: Related Workmentioning

confidence: 99%

Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation

Zhan

Chen

Sánchez-Sinencio

2019

IEEE Trans. VLSI Syst.

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This work is based on the vision that the ultimate power integrity and efficiency may be best achieved via a heterogeneous chain of voltage processing starting from onboard switching voltage regulators (VRs), to on-chip switching VRs, and finally to networks of distributed on-chip linear VRs. As such, we propose a heterogeneous voltage regulation (HVR) architecture encompassing regulators with complimentary characteristics in response time, size, and efficiency. By exploring the rich heterogeneity and tunability in HVR, we develop systematic workload-aware power management policies to adapt heterogeneous VRs with respect to workload change at multiple temporal scales to significantly improve system power efficiency while providing a guarantee for power integrity. The proposed techniques are further supported by hardware-accelerated machine learning (ML) prediction of nonuniform spatial workload distributions for more accurate HVR adaptation at fine time granularity. Our evaluations based on the PARSEC benchmark suite show that the proposed adaptive three-stage HVR reduces the total system energy dissipation by up to 23.9% and 15.7% on average compared with the conventional static two-stage voltage regulation using off-chip and on-chip switching VRs. Compared with the three-stage static HVR, our runtime control reduces system energy by up to 17.9% and 12.2% on average. Furthermore, the proposed ML prediction offers up to 4.1% reduction of system energy.

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“…Previous works have proposed ways to deal with such variability by using adaptive guardbanding, adaptive reliability management, and novel task mapping techniques [5,[19][20][21], however none of them manage hardware unpredictability in a holistic manner to enable steady co-existence of critical, sensitive, and best effort tasks in the same system -which is one of our key contributions in CHIPS-AHOy.…”

Section: Related Work and Motivationmentioning

confidence: 99%

CHIPS-AHOy

Mück

Fröhlich

Gracioli

et al. 2018

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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Virtual machines (VMs) are being deployed on embedded systems to integrate multiple applications with different run-time requirements on the same physical platform. In scenarios such as autonomous vehicles, these virtualized platforms must handle varying application requirements -from strict temporal predictability to high performance -while simultaneously satisfying disparate constraints such as energy efficiency, thermal bounds, and system lifetime. To address these challenges we present CHIPS-AHOy, a prediCtable HolIstic cyber-PhySicAl HypervisOr that integrates VM isolation mechanisms with novel resource allocation approaches within a holistic observe-decide-adapt loop to achieve run-time predictability and simultaneously manage energy, thermal and wearout constraints. We present experimental results on several realistic MPSoC platforms that demonstrate the ability of CHIPS-AHOy to achieve predictable operation while conserving energy, managing temperature and extending system lifetime.

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Adaptive guardband scheduling to improve system-level efficiency of the POWER7+

Cited by 46 publications

References 35 publications

ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance

ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance

Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation

CHIPS-AHOy

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