Adaptive Mapping for Multiple Applications on Parallel Architectures

Assayad, Ismail; Girault, Alain

doi:10.1007/978-3-319-68179-5_51

Cited by 2 publications

(1 citation statement)

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“…126 The survey also classifies mapping techniques into static and 127 dynamic domains. A comprehensive survey on application 128 mapping techniques and their comparative analysis have been 129 presented in [18]. The survey discusses the classification of…”

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A Survey on Dynamic Application Mapping Approaches for Real-Time Network-on-Chip-Based Platforms

Saleem,

Hussain,

Amin

et al. 2023

IEEE Access

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Network-on-Chip (NoC) has been unfolded as a superior alternative for integrating a considerably greater extent of cores on a single chip. Recently, multi-core systems have become prevalent because of the increased processing demands for high-performance embedded applications. Application mapping techniques play a significant role in enhancing the extensive performance of such complex multicore platforms. Developing and implementing efficient application mapping techniques are required for system design to meet the demand of such complicated multi-core systems. The paper primarily focuses on dynamic application mapping techniques, classifying them into a number of subcategories. It highlights such approaches and techniques that aim to enhance the performance of the NoC-based systems by optimizing them in terms of communication cost, latency, energy consumption, power, execution, and computational time. Future challenges, trends, and simulation tools have also been spotlighted. INDEX TERMSNetwork-on-Chip, Application mapping, System-on-Chip, VOPD.I. INTRODUCTION D UE to the rise in complexity of embedded This is some system devices, system-on-chip (SoC) incorporating the numerous processing cores on a single chip to perform various functions is the primary paradigm of today's digital world. The SoC uses a shared medium bus to communicate intellectual property (IP) cores and is widely utilized in domain-specific devices [1], [2], such as aerospace, medical sciences, microprocessors-based technology, and wireless communications. Due to the higher density of components in SoC, the implementation of a shared-bus architecture is getting complicated. As the number of cores increases on the chip, the performance is not enhanced and scaled by the increased processing cores due to the limitations of the shared-bus architecture. Network-on-chip (NoC) has emerged as a feasible substitute to cater to the new inter-core communication demands of the growing number of 17 components on a chip and faster communication between 18 the cores [3]. NoC architecture is considered a part of or 19 a subset of SoC-based technology [4]. NoC uses IP cores 20 connected with the routers and inter-switch links [5], and 21 the communication between the cores is done by transferring 22 packets with these routers and links. Messages are divided 23 into smaller packets to be transmitted between various cores 24 that allow for the efficient use of network resources. NoC 25 employs a routing algorithm for the determination of the 26 path that each packet follows from the source to the destina-27 tion. Various switching techniques are developed to transfer 28 packets such as circuit and packet switching. A physical 29 path from source to destination is reserved before the data 30 transmission in circuit switching. While in packet switching, 31 each message is partitioned into fixed-length packets which 32

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confidence: 99%