Adaptive processor architecture - invited paper

Huebner, M.; Goehringer, Diana; Tradowsky, Carsten; Henkel, Joerg; Becker, J.

doi:10.1109/samos.2012.6404181

Cited by 3 publications

(2 citation statements)

References 33 publications

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“…An extreme way to do so, is e.g. to insert the reconfiguration port of the FPGA directly into the data path of the processor [13].…”

Section: Processing Elementsmentioning

confidence: 99%

Reconfigurable Multiprocessor Systems

Göhringer

2014

SIGARCH Comput. Archit. News

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Novel solutions are needed to fulfill the increasing demands of embedded systems, i.e. lowering the energy consumption, increasing the performance, reducing the development time and keeping the costs as low as possible. In addition, there exist several applications, which require runtime adaptations of the algorithms based on the connection to its environment. These challenges can be solved by using reconfigurable Multiprocessor Systems-on-Chip (MPSoCs), which can adapt the hardware as well as the software to the application requirements and therefore achieve a high computational efficiency as well as a high flexibility. However, the development, the programming and the operation of such flexible and heterogeneous systems is very complex as the many criteria (Performance, power consumption, costs, development time, runtime adaptations, etc.) open a huge design space. In this paper an overview of the challenges faced when developing runtime adaptive MPSoCs is given. Finally, for each challenge a survey of possible solutions are presented.

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“…An extreme way to do so, is e.g. to insert the reconfiguration port of the FPGA directly into the data path of the processor [13].…”

Section: Processing Elementsmentioning

confidence: 99%

Reconfigurable Multiprocessor Systems

Göhringer

2014

SIGARCH Comput. Archit. News

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“…Michael, et al [362] introduce a novel methodology to adapt the microarchitecture of a processor at run-time. The goal is to tailor the internal architecture to the requirements of an application and the data to be processed.…”

Section: Adaptive Processor Related Work Recapmentioning

confidence: 99%

A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

Ali¹

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The reconfigurable computing (RC) aims to combine the flexibility of General-Purpose Processor (GPP) with performance of Application Specific Integrated Circuits (ASIC). There are several architectures proposed since RC’s inception in 1960s, but all have failed to become mainstream. The main factor preventing RC to become common practice is its requirement for implementers of algorithms (programmers) to be familiar with hardware design. In RC, a hardened processor cooperates with a dynamic reconfigurable Hardware Accelerator (HA) which is implemented on Field-Programmable Gate Array (FPGA). The HA implements crucial software kernel on hardware to increase performance and its design demands digital circuit expertise. In this paper a novel RC architecture is proposed that keeps the decades old programming practices intact while harnessing the power of HA. The architecture uses LLVM compiler infrastructure to receive an algorithm and then outputs the equivalent machine language, it then finds the most frequent instruction pairs and generates equivalent RC circuit called “Miniature Accelerator (MA)”. The instruction pairs are dynamically removed from pipeline and MA computed result replaces them in parallel. To demonstrate the concept the Fast Fourier Transform (FFT) algorithm which is core Digital signal processing (DSP) kernel is written in C and then executed on an ARM Cortex-M0. The execution of FFT function is improved by 14.12%. The proposed adaptive processor is fully backward compatible, compilation is automated, and no modification of exiting software or established programming paradigms is required.

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