Adaptive real-time DSP acceleration for SoC applications

Abstract

This paper investigates VLSI architectures for digital processing (DSP) functions amenable to low energy operation with scalable performance for H.265 high efficiency video coding (HEVC) applications. First, we describe and experimentally evaluate a novel adaptive computing fabric. Second, we propose an energy-efficient method to scale the performance of the fabric for large images or for meeting stringent real-time computation requirements. A series of tradeoffs for exploiting efficiently the application space for general purpose DSP acceleration are proposed. We experimentally show how the proposed computing fabric is reusable for Filters, FFT and DCT acceleration with a scalable throughput. We report on the design and implementation of the fabric on a Xilinx FPGA device and show how regulatedparallelism augmented with in-memory processing techniques impact performance and power efficiency. The FPGA prototype demonstrates a sustained throughput exceeding 10Gbps irrespective of the kernel and image size for H.265 HEVC applications.

Hardware acceleration of genomics data analysis: challenges and opportunities

“…The reliance on global memory access results in a substantial increase in system delays as the system scales in both volumes of data and processing cores. To successfully address the issue of scalability with the ability to maintain a high throughput of data from memory to processing cores, researchers such as Nsame et al (2014) and Sarkar et al (2010) explored the use of the Networks-on-Chip (NoC) interconnect strategy in many applications.…”