Adaptive Thread Scheduling in Chip Multiprocessors

Akturk, Ismail; Öztürk, Özcan

doi:10.1007/s10766-019-00637-y

Cited by 5 publications

(11 citation statements)

References 27 publications

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“…Akturk and Ozturk 6 also proposed similar solutions: they calculate the inter‐thread contention using scores not available in current processors. Another drawback of their mechanism is that it considers only inter‐thread cache contention suitable for memory‐bound applications.…”

Section: Discussionmentioning

confidence: 99%

“…Akturk and Ozturk 6 propose a cache‐hierarchy‐aware scheduler for multiple sequential applications, which balances the number of accesses to the L1 cache, reducing the number of evictions on shared caches which eventually limits the performance. Akturk and Ozturk work is very similar to Settle et al; 11 the main differences are that Akturk considers only L1 cache while Settle correlated different cache levels and metrics with the IPC of several applications.…”

Section: Related Workmentioning

confidence: 99%

“…Previous research has identified communication and cache memory contention on SMT processors as one of the main performance bottlenecks 6‐10 . By analyzing multiple single‐thread multiprogram workloads, the authors propose techniques to mitigate such effects, improving performance.…”

Section: Introductionmentioning

confidence: 99%

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Mitigating execution unit contention in parallel applications using instruction‐aware mapping

Serpa

Cruz

Diener

et al. 2021

Concurrency and Computation

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Parallel applications running on simultaneous multithreading (SMT) processors naturally compete for execution units when their threads are mapped to the same core. This issue is further aggravated when such threads execute similar instructions that stress the same execution unit type, making their execution to behave very similarly as if the threads were running sequentially. This, in turn, will lead to performance degradation and underutilization of hardware resources. This work proposes a completely transparent framework (no modifications to the source code are necessary) that automatically maps threads of multiple parallel applications on SMT processors.The framework focuses on improving performance by mitigating the contention on execution units, considering each thread's instruction types, which are detected at runtime by our framework. Results show performance gains of 21% (geometric mean), compared to the native scheduler of the operating system.

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Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Mitigating execution unit contention in parallel applications using instruction‐aware mapping

Serpa

Cruz

Diener

et al. 2021

Concurrency and Computation

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show abstract

“…Diferente deles, também consideramos unidades de execução, como branch, inteiro e ponto flutuante. Akturk et al [Akturk and Ozturk 2019] propõem um escalonador que mapeia threads de uma forma que minimiza o número de acessos a cache L1 e reduz o número de evictions em caches compartilhadas que eventualmente limitam o desempenho. Eles melhoram o desempenho do benchmark PARSEC [Bienia 2011] em até 12,6%.…”

Section: Trabalhos Relacionadosunclassified

“…Pesquisas anteriores identificaram a contenção na memória principal e nas memórias cache dos processadores SMT como um dos principais gargalos de desempenho [Akturk and Ozturk 2019, Choi and Yeung 2009, Cruz et al 2018, Feliu et al 2016, Serpa et al 2019a, Serpa et al 2019b]. Assim, utilizando múltiplas aplicações sequenciais, os autores propõem técnicas para mitigar esses efeitos, melhorando o desempenho.…”

Section: Introductionunclassified

Atenuando a Contenção nas Unidades de Execução com Mapeamento Instruction-Aware

Serpa

Cruz

Diener

et al. 2020

Anais Do XXI Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2020)

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Aplicações paralelas executadas em processadores SMT (Simultaneous Multithreading) competem por unidades de execução. O problema ﬁca ainda pior, quando as threads executam instruções semelhantes, como por exemplo de ponto ﬂutuante, inteiro, load e store. Nesses casos, o mesmo tipo de instrução é despachado para execução, o que leva a perdas de desempenho devido a contenção nessas unidades. Este trabalho tem como objetivo fornecer um mecanismo para mapeamento de múltiplas aplicações paralelas em processadores SMT. O mecanismo foca em melhorar o desempenho, mitigando a contenção nas unidades de execução ao executar aplicações paralelas. Para tanto, threads que estressam as mesmas unidades de execução são mapeadas em núcleos diferentes. Os resultados mostram ganhos de desempenho de 29,1% e 17,4%, em média, quando comparado com o escalonador do sistema operacional Linux e com um mapeamento Round-robin.

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Efficient thread‐to‐core mapping alternatives for application‐level redundant multithreading

Arslan

Ünsal

2023

Concurrency and Computation

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SummaryRedundant multithreading (RMT) is an effective thread‐level replication method to improve the reliability requirements of applications. Although it significantly improves the robustness of applications, it comes with additional performance overhead since the redundant threads might share the same core resources. In our previous study [Efficient selective replication of critical code regions for SDC mitigation leveraging redundant multithreading. J Supercomput 2021;77:14130‐14160], we presented an efficient software‐level RMT approach, where we execute the most critical code regions with three threads to correct errors. In this study, we focus on further improving the performance of our software‐level RMT method by presenting a set of different thread‐to‐core mapping alternatives. We provide different static mapping methods, which require preliminary information about the applications, such as execution time, instruction‐per‐cycle (IPC), or cache usage patterns, and a set of dynamic mapping methods, which map threads to cores dynamically at runtime without requiring any additional information. The dynamic mapping methods decide which threads are mapped to which cores at each scheduling point based on the IPC, cache miss rate, or cache access values of each thread as well as each core. Experimental results show that the dynamic mapping method, which maps threads to cores based on IPC values, outperforms all other static and dynamic methods. It also outperforms our baseline model, where the operating system handles the thread‐to‐core mappings by 8%, 7%, and 20% based on average speedup, harmonic speedup, and mean slowdown metrics.

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Adaptive Thread Scheduling in Chip Multiprocessors

Cited by 5 publications

References 27 publications

Mitigating execution unit contention in parallel applications using instruction‐aware mapping

Mitigating execution unit contention in parallel applications using instruction‐aware mapping

Atenuando a Contenção nas Unidades de Execução com Mapeamento Instruction-Aware

Efficient thread‐to‐core mapping alternatives for application‐level redundant multithreading

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