Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation

Abellán, José Luis; Coskun, Ayse K.; Gu, Anjun; Jin, Warren; Joshi, Ajay; Kahng, Andrew B.; Klamkin, Jonathan; Morales, Cristian; Recchio, John; Srinivas, Vaishnav; Zhang, Tiansheng

doi:10.1109/tcad.2016.2600238

Cited by 22 publications

(4 citation statements)

References 36 publications

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“…The thermal variations due to active electrical circuits within memory lowers the reliability of the MRR operation. Such a design calls for active thermal and power management in OPCM, which contributes to a power overhead of 10 − 30W [3]. Furthermore, using silicon-photonic links in combination with OPCM requires additional E-O and O-E conversions with this EPCM architecture that exacerbate the above discussed problems.…”

Section: Motivationmentioning

confidence: 99%

“…For a 2GB 4-bit OPCM array with 8 banks, a single bank consists of 1024 tiles with 32 cells/tile and a row and column of MRRs as shown in Figure 4b. 3 A bank, therefore, is composed of 1024 × 32 GSTs along a row/column with (1024 × 32 − 1) × 50nm of separation between GSTs, and a single row/column of MRRs at the beginning. Using the dimensions of these optical devices listed in Table IV, we calculate the area of a 2GB OPCM array and its bit density and report it in Table V.…”

Section: Area Analysis Of the Opcm Arraymentioning

confidence: 99%

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Architecting Optically-Controlled Phase Change Memory

Narayan¹,

Thonnart²,

Vivet³

et al. 2021

Preprint

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Phase Change Memory (PCM) is an attractive candidate for main memory as it offers non-volatility and zero leakage power, while providing higher cell densities, longer data retention time, and higher capacity scaling compared to DRAM. In PCM, data is stored in the crystalline or amorphous state of the phase change material. The typical electrically-controlled PCM (EPCM), however, suffers from longer write latency and higher write energy compared to DRAM and limited multi-level cell (MLC) capacities. These challenges limit the performance of data-intensive applications running on computing systems with EPCMs.Recently, researchers demonstrated optically-controlled PCM (OPCM) cells, with support for 5 bits/cell in contrast to 2 bits/cell in EPCM. These OPCM cells can be accessed directly with optical signals that are multiplexed in high-bandwidthdensity silicon-photonic links. The higher MLC capacity in OPCM and the direct cell access using optical signals enable an increased read/write throughput and lower energy per access than EPCM. However, due to the direct cell access using optical signals, OPCM systems cannot be designed using conventional memory architecture. We need a complete redesign of the memory architecture that is tailored to the properties of OPCM technology.This paper presents the design of a unified network and main memory system called COSMOS that combines OPCM and silicon-photonic links to achieve high memory throughput. COSMOS is composed of a hierarchical multi-banked OPCM array with novel read and write access protocols. COSMOS uses an Electrical-Optical-Electrical (E-O-E) control unit to map standard DRAM read/write commands (sent in electrical domain) from the memory controller on to optical signals that access the OPCM cells. Our evaluation of a 2.5D-integrated system containing a processor and COSMOS demonstrates 2.14× average speedup across graph and HPC workloads compared to an EPCM system. COSMOS consumes 3.8× lower read energy-per-bit and 5.97× lower write energy-per-bit compared to EPCM. COSMOS is the first non-volatile memory that provides comparable performance and energy consumption as DDR4 in addition to increased bit density, higher area efficiency and improved scalability.

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Section: Motivationmentioning

confidence: 99%

Section: Area Analysis Of the Opcm Arraymentioning

confidence: 99%

Architecting Optically-Controlled Phase Change Memory

Narayan¹,

Thonnart²,

Vivet³

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

show abstract

“…With the growing requirements of chip computing performance and multitasking simultaneous processing capability, electrical networks-on-chip (ENoCs) cannot meet the needs of MPSoCs development due to the time delay, bandwidth, and power consumption problems [4]. Optical networks-on-chip (ONoCs), which can break through these bottlenecks, have been proven an effective method to solve the problems faced by ENoCs [5][6][7][8][9]. ONoCs combine both the characteristics of the electrical interconnect layer, which implements arbitration control, and the optical layer to transfer data [10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Crosstalk Analysis and Performance Evaluation for Torus-Based Optical Networks-on-Chip Using WDM

Song

Xie

et al. 2020

Micromachines

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Insertion loss and crosstalk noise will influence network performance severely, especially in optical networks-on-chip (ONoCs) when wavelength division multiplexing (WDM) technology is employed. In this paper, an insertion loss and crosstalk analysis model for WDM-based torus ONoCs is proposed to evaluate the network performance. To demonstrate the feasibility of the proposed methods, numerical simulations of the WDM-based torus ONoCs with optimized crossbar and crux optical routers are presented, and the worst-case link and network scalability are also revealed. The numerical simulation results demonstrate that the scale of the WDM-based torus ONoCs with the crux optical router can reach 6 × 5 or 5 × 6 before the noise power exceeds the signal power, and the network scale is 5 × 4 in the worst case when the optimized crossbar router is employed. Additionally, the simulated results of OptiSystem reveal that WDM-based torus ONoCs have better signal transmission quality when using the crux optical router, which is consistent with previous numerical simulations. Furthermore, compared with the single-wavelength network, WDM-based ONoCs have a great performance improvement in end-to-end (ETE) delay and throughput according to the simulated results of OPNET. The proposed network analysis method provides a reliable theoretical basis and technical support for the design and performance optimization of ONoCs.

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“…Nonetheless, this technique for thermal tuning power consumption may negatively affect the bene ts of PNoC in terms of energy e ciency. In [13], a new frequency-align workload allocation policy, along with an Adaptive Frequency Tuning (AFT) policy, which can reduce the thermal power consumption of PNoCs, is presented. Frequency alignment uses thread allocation and thread migration to control the thermal, in order to match the photonic frequencies of the MRR loops in each photonic link.…”

mentioning

confidence: 99%

A Thermal Aware Application Mapping Algorithm for Photonic networks-on-chip

Ghafori

Reza

Mirzaee

2022

Preprint

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Photonic Network on Chip(PNoC) is a promising solution to overcome scalability and power consumption challenges in the traditional Network on Chip(NoC), with high bandwidth and low latency communication. Thermal sensitivity is one of the main problems in PNoC network. Because of the thermal sensitivity of photonic devices, thermal effects can cause the operation becomes incorrect or inaccurate, same as Laser power efficiency degradation, wavelength shifting, power loss due to wavelength mismatch, and switching disorders. Therefore, the goal of this study is set to present a suitable new mapping algorithm, which aims to Thermal distribution and maximum reduction thermal of PNoC. The main parameter that affects power consumption and thermal is a maximum power loss, maximum number of WDM channels and maximum communication thermal correlation. By increasing the amount of maximum power loss and the maximum number of WDM channels, the power of the signal in the source must be increased, which leads to an increase in thermal PNoC. In this paper, we modelled thermal parameters and suggested a fitness function to evaluate application mapping algorithms based on genetic algorithms. Based on evaluation results, the minimum thermal improvement is 23% in GA mapping with different W Coefficient and 46% improvement compared to the Nmap algorithm.

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Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation

Cited by 22 publications

References 36 publications

Architecting Optically-Controlled Phase Change Memory

Architecting Optically-Controlled Phase Change Memory

Crosstalk Analysis and Performance Evaluation for Torus-Based Optical Networks-on-Chip Using WDM

A Thermal Aware Application Mapping Algorithm for Photonic networks-on-chip

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