Adding instruction cache effect to schedulability analysis of preemptive real-time systems

Busquets-Mataix, J.V.; Serrano, Juan José; Ors, R.; Gil, P.; Wellings, Andy

doi:10.1109/rttas.1996.509537

Cited by 113 publications

(107 citation statements)

References 12 publications

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“…There is an increase in the execution time of bar because foo reused bar's cache blocks, forcing bar to fetch the blocks again after resuming. This delay (total 1ms) is the cache-related preemption delay (CRPD) [Busquets-Mataix et al 1996].…”

Section: Real-time Systems Sharing the Cachementioning

confidence: 99%

“…The crudest approach to CRPD analysis is to assume that every preemption causes a complete flush of the entire cache; a safe but often imprecise assumption. Successively more precise estimates have been achieved by researchers [Busquets-Mataix et al 1996;Lee et al 1998;Staschulat et al 2005;Tan and Mooney 2007;Altmeyer and Maiza 2010;Altmeyer et al 2011;2012]. Estimates are generated by examining which cache blocks are definitely reused by lower-priority tasks (useful cache blocks) and which cache blocks are accessed by higher-priority tasks (evicted cache blocks).…”

Section: Real-time Systems Sharing the Cachementioning

confidence: 99%

“…The earliest CRPD analyses used only ECB sets to determine a pessimistic upper bound on the CRPD [Busquets-Mataix et al 1996]. Subsequent analyses introduced UCB sets to the analysis [Tan and Mooney 2007;Altmeyer and Maiza 2010], which can be used in different ways (e.g.…”

Section: Reducing Crpd By Better Analysismentioning

confidence: 99%

“…In this paper, we apply earlier work on explicit reservation of local memory [Whitham and Audsley 2012] to the problem of reducing worst-case cache-related preemption delay (CRPD) [Busquets-Mataix et al 1996]. CRPD is observed in preemptive multitasking systems.…”

Section: Introductionmentioning

confidence: 99%

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Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system

Whitham

Audsley

Davis

2014

ACM Trans. Embed. Comput. Syst.

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We describe and evaluate explicit reservation of cache memory to reduce the cache-related preemption delay (CRPD) observed when tasks share a cache in a preemptive multitasking hard real-time system. We demonstrate the approach using measurements obtained from a hardware prototype, and present schedulability analyses for systems that share a cache by explicit reservation. These analyses form the basis for a series of experiments to further evaluate the approach. We find that explicit reservation is most useful for larger task sets with high utilization. Some task sets cannot be scheduled with a conventional cache, but are schedulable with explicit reservation.

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Section: Real-time Systems Sharing the Cachementioning

confidence: 99%

Section: Real-time Systems Sharing the Cachementioning

confidence: 99%

Section: Reducing Crpd By Better Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system

Whitham

Audsley

Davis

2014

ACM Trans. Embed. Comput. Syst.

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“…Our approach eliminates cache penalties due to cold-starting the cache after a context switch. Thus, classical non-cache sensitive schedulability analyses should be used rather than their cache-sensitive versions, CUA [Basumallick and Nielsen 1994] and CRTA [Busquets-Mataix et al 1996]. …”

Section: Task Model and Schedulability Analysismentioning

confidence: 99%

Data cache locking for tight timing calculations

Vera

Lisper

Xue

2007

ACM Trans. Embed. Comput. Syst.

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Caches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs exhibit sufficient data locality. In addition, caches are a source of unpredictability, resulting in programs sometimes behaving in a different way than expected.Detailed information about the number of cache misses and their causes allows us to predict cache behavior and to detect bottlenecks. Small modifications in the source code may change memory patterns, thereby altering the cache behavior. Code transformations which take the cache behavior into account might result in a high cache performance improvement. However, cache memory behavior is very hard to predict, thus making the task of optimizing and timing cache behavior very difficult.This article proposes and evaluates a new compiler framework that times cache behavior for multitasking systems. Our method explores the use of cache partitioning and dynamic cache locking to provide worst-case performance estimates in a safe and tight way for multitasking systems. We use cache partitioning, which divides the cache among tasks to eliminate inter-task cache interferences. We combine static cache analysis and cache locking mechanisms to ensure that all intra-task conflicts, and consequently, memory access times, are exactly predictable.The results of our experiments demonstrate the capability of our framework to describe cache behavior at compile time. We compare our timing approach with a system equipped with a nonpartitioned but statically locked data cache. Our method outperforms static cache locking for all analyzed task sets under various cache architectures, demonstrating that our fully predictable scheme does not compromise the performance of the transformed programs.

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