Adding Security to Networks-on-Chip using Neural Networks

Madden, Kyle; Harkin, Jim; McDaid, Liam; Nugent, Chris

doi:10.1109/ssci.2018.8628832

Cited by 23 publications

(17 citation statements)

References 29 publications

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“…• HTs can be inserted through gate-level manipulation of the NoC netlist by an adversary designer [32], [33]. • EDA tools can also target companies' products to insert HTs for defamation purposes.…”

Section: Taxonomy and Attacksmentioning

confidence: 99%

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

et al. 2021

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Network-on-Chips (NoCs) have been widely used as a scalable communication solution in the design of multiprocessor system-on-chips (MPSoCs). NoCs manage communications between on-chip Intellectual Property (IP) cores and allow processing cores to achieve higher performance by outsourcing their communication tasks. NoC paradigm is based on the idea of resource sharing where hardware resources, including buffers, communication links, routers, etc., are shared between all IPs of the MPSoC. In fact, the data being routed by each NoC router might not be related to the router's local core. Such a utilization-centric design approach can raise security issues in MPSoCs-based designs, e.g., integrity and confidentiality of the data being routed in an NoC might be compromised by unauthorized accesses/modifications of intermediate routers. Many papers in the literature have discovered and addressed security holes of NoCs, aiming at improving the security of the NoC paradigm. However, to the best of our knowledge, there is no solid survey study on the security vulnerabilities and countermeasures for NoCs. This paper will review security threats and countermeasures proposed so far for wired NoCs, wireless NoCs, and 3D NoCs. The paper aims at giving the readers an insight into the attacks and weaknesses/strengths of countermeasures.

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Section: Taxonomy and Attacksmentioning

confidence: 99%

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

et al. 2021

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“…Authors in [11] propose firewalls between routers, monitoring occupation time of links. The approach presented in [12] applies a spiking neural network for detecting an abnormal amount of communication requests. The work in [13] uses distributed monitors that threshold the amount of received packets in NIs.…”

Section: B Dos Attack Detectionmentioning

confidence: 99%

Lightweight Monitoring Scheme for Flooding DoS Attack Detection in Multi-Tenant MPSoCs

Chaves

Sepúlveda

Hollstein

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) within scalable multi-tenant systems, such as fog/cloud computing, faces the challenge of potential attacks originated by the execution of malicious tasks. Flooding Denialof-Service (FDoS) attacks are one of the most common and powerful threats for Network-on-Chip (NoC)-based MPSoCs. Since, by overwhelming the NoC, the system is unable to forward legitimate traffic. However, the effectiveness of FDoS attacks depend on the NoC configuration. Moreover, designing a secure MPSoC capable of detecting such attacks while avoiding excessive power/energy and area costs is challenging. To this end, we present two contributions. First, we demonstrate two types of FDoS attacks: based on the packet injection rate (PIR-based FDoS) and based on the packet's payload length (PPL-based FDoS). We show that fair round-robin NoCs are intrinsically protected against PIR-based FDoS. Instead, PPL-based FDoS attacks represent a real threat to MPSoCs. Second, we propose a novel lightweight monitoring method for detecting communication disruptions. Simulation and synthesis results show the feasibility and efficiency of the presented approach.

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“…Madden et al presented a spiking neural network (SNN)based HT detection approach that was designed to detect DoS attacks through abnormal traffic patterns in NoC data [111]. They first extracted the spatial and temporal features of digital data exchanged across traffic links between adjacent routers.…”

Section: -Implantation Preventionmentioning

confidence: 99%

“…Note that in addition to Markv distance-based CA, unsupervised learning models only require testing datasets as input such as in [70], [85], [91], [111], and [114] (see Tables 15 -18). Some researchers use sample datasets with labels as unlabeled data, for example, the work of Cui et al in [90], to train the learning models and then validate them using the testing datasets.…”

Section: ) Effect Of the Training And Testing Dataset Sizesmentioning

confidence: 99%

A Survey on Machine Learning Against Hardware Trojan Attacks: Recent Advances and Challenges

et al. 2020

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The remarkable success of machine learning (ML) in a variety of research domains has inspired academic and industrial communities to explore its potential to address hardware Trojan (HT) attacks. While numerous works have been published over the past decade, few survey papers, to the best of our knowledge, have systematically reviewed the achievements and analyzed the remaining challenges in this area. To fill this gap, this article surveys ML-based approaches against HT attacks available in the literature. In particular, we first provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture. Based on the review, we further discuss the lessons learned in and challenges arising from previous studies. Despite current work focusing more on chip-layer HT problems, it is notable that novel HT threats are constantly emerging and have evolved beyond chips and to the component, device, and even behavior layers, therein compromising the security and trustworthiness of the overall hardware ecosystem. Therefore, we divide the HT threats into four layers and propose a hardware Trojan defense (HTD) reference model from the perspective of the overall hardware ecosystem, therein categorizing the security threats and requirements in each layer to provide a guideline for future research in this direction.

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Adding Security to Networks-on-Chip using Neural Networks

Cited by 23 publications

References 29 publications

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

Lightweight Monitoring Scheme for Flooding DoS Attack Detection in Multi-Tenant MPSoCs

A Survey on Machine Learning Against Hardware Trojan Attacks: Recent Advances and Challenges

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