ADDLL for Clock-Deskew Buffer in High-Performance SoCs

Park, Jung Hyun; Jung, Dong-Hoon; Ryu, Koungmin

doi:10.1109/tvlsi.2012.2210742

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Cited by 4 publications

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A multimode DLL with trade-off between multiphase and static phase error

Zhang

Zhu

et al. 2014

J. Semicond.

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A multimode DLL with trade-off between multiphase and static phase error is presented. By adopting a multimode control circuit to regroup the delay line, a better static phase error performance can be achieved while reducing the number of output phases. The DLL accomplishes three operation modes: mode1 with a four-phase output, mode2 with a two-phase output and a better static phase error performance, and mode3 with only a onephase output but the best static phase error performance. The proposed DLL has been fabricated in 0.13 m CMOS technology and measurement results show that the static phase errors of mode1, mode2 and mode3 are -18.2 ps, 11.8 ps and 6:44 ps, respectively, at 200 MHz. The measured RMS and peak-to-peak jitters of mode1, mode2 and mode3 are 2.0 ps, 2.2 ps, 2.1 ps and 10 ps, 9.3 ps, 10 ps respectively.

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