Addressing characterization methods for memory contention aware co-scheduling

Blanche, Andreas de; Lundqvist, Thomas

doi:10.1007/s11227-014-1374-8

Cited by 19 publications

(12 citation statements)

References 29 publications

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“…The rest of this section presents prior efforts which identify, quantify or model the applications' performance due to shared resource contention. Slowdown based methods -De Blanche et al [12,13] propose a slowdown based characterization method to estimate the applications' slowdown when sharing the memory bus. Their sensitivity curve is obtained using synthesized memory traffic and the contentiousness is found using performance counters.…”

Section: Related Workmentioning

confidence: 99%

“…Using this specific configuration to create the sensitivity curve, we maintain the same static read/write ratio and computing characteristics used by the authors in their work. Another point regarding the sensitivity curve is that [12] and [13] do not specify whether the values of the x-axis are the maximum bandwidth or the interfering bandwidth in contention. We assumed the same approach applied in our work, using the maximum bandwidth achieved during the interfering test.…”

Section: Comparison With Memgenmentioning

confidence: 99%

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Contention-aware application performance prediction for disaggregated memory systems

Zacarias

Nishtala

Carpenter

2020

Proceedings of the 17th ACM International Conference on Computing Frontiers

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Disaggregated memory has recently been proposed as a way to allow flexible and fine-grained allocation of memory capacity to compute jobs. This paper makes an important step towards effective resource allocation on disaggregated memory systems. Specifically, we propose a generic approach to predict the performance degradation due to sharing of disaggregated memory. In contrast to prior work, cache capacity is not shared among multiple applications, which removes a major contributor to application performance. For this reason, our analysis is driven by the demand for memory bandwidth, which has been shown to have an important effect on application performance. We show that profiling the application slowdown often involves significant experimental error and noise, and to this end, we improve the accuracy by linear smoothing of the sensitivity curves. We also show that contention is sensitive to the ratio between read and write memory accesses, and we address this sensitivity by building a family of sensitivity curves according to the read/write ratios. Our results show that the methodology predicts the slowdown in application performance subject to memory contention with an average error of 1.19% and max error of 14.6%. Compared with stateof-the-art, the relative improvements are almost 24% on average and 33% for the worst case. CCS CONCEPTS • Computing methodologies → Modeling methodologies.

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Section: Related Workmentioning

confidence: 99%

Section: Comparison With Memgenmentioning

confidence: 99%

Contention-aware application performance prediction for disaggregated memory systems

Zacarias

Nishtala

Carpenter

2020

Proceedings of the 17th ACM International Conference on Computing Frontiers

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“…Only then can it be motivated from the compute centers' point of view for an optimization of the system workload. Although different proposals exist that use prediction models for efficient co‐scheduling,() they are usually based on empirical slow‐down analyses. In contrast, we propose a scheduling scheme based on an online analysis of the applications' resource consumption.…”

Section: Related Workmentioning

confidence: 99%

Prospects and challenges of virtual machine migration in HPC

Pickartz

Clauss

Breitbart

et al. 2018

Concurrency and Computation

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Summary The continuous growth of supercomputers is accompanied by increased complexity of the intra‐node level and the interconnection topology. Consequently, the whole software stack ranging from the system software to the applications has to evolve, eg, by means of fault tolerance and support for the rising intra‐node parallelism. Migration techniques are one means to address these challenges. On the one hand, they facilitate the maintenance process by enabling the evacuation of individual nodes during runtime, ie, the implementation of fault avoidance. On the other hand, they enable dynamic load balancing for an improvement of the system's efficiency. However, these prospects come along with certain challenges. On the process level, migration mechanisms have to resolve so‐called residual dependencies to the source node, eg, the communication hardware. On the job level, migrations affect the communication topology, which should be addressed by the communication stack, ie, the optimal communication path between a pair of processes might change after a migration. In this article, we explore migration mechanisms for HPC and discuss their prospects as well as the challenges. Furthermore, we present solutions enabling their efficient usage in this domain. Finally, we evaluate our prototype co‐scheduler leveraging migration for workload optimization.

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“…Lee et al [7] investigated the interactions between prefetchers and on-chip networks, exploiting the synergy of these two components in multi-cores to reduce the traffic generated by the prefetchers. Blanche and Lundqvist [11] evaluated the prediction accuracy and co-scheduling performance of four state-of-the-art characterization methods for memory aware (co-) scheduling. Zhang [14] proposed a load balancing task scheduling algorithm based on weighted random and feedback mechanisms to eliminate system bottlenecks and balance loads dynamically.…”

Section: Related Workmentioning

confidence: 99%

“…As hardware moves towards integrated memory controllers and higher bandwidth, selecting prefetchers properly will play a significant role in optimizing system performance. Recent works [11][12][13][14] on the topic of performance degradation in multi-core systems focused on contention for cache space and bus bandwidth when applications share the last level cache (LLC). It is well known that many factors contribute to performance degradation when threads share an LLC.…”

Section: Introductionmentioning

confidence: 99%

Performance Improvements by Deploying L2 Prefetchers with Helper Thread for Pointer-Chasing Applications

Huang¹

2018

IJPE

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Modern processor micro-architecture offers advanced prefetch mechanisms that are designed to effectively hide memory latency and improve application performance. However, pointer-chasing applications employing linked data structures expose a memory latency problem that is difficult to deal with by using hardware prefetchers. It is promising that helper threaded prefetching based on Chip Multiprocessor is an effective method for reducing the memory latency of accesses to linked data structures. In this paper, we first illustrated two L2 prefetchers on Chip Multiprocessor and two different helper threaded prefetching techniques for pointer-chasing applications. Then, we revealed the limitations of L2 prefetchers for pointer-intensive applications after applying two different threaded prefetching techniques. Finally, we optimized the deployment of L2 prefetchers with two different threaded prefetching techniques for pointer-chasing applications. The experimental results indicate that L2 prefetchers' effectiveness on helper threads depends on the memory access pattern of the targeted applications, and the optimized deployment of L2 prefetchers further improves the performance of pointer-intensive applications.

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Addressing characterization methods for memory contention aware co-scheduling

Cited by 19 publications

References 29 publications

Contention-aware application performance prediction for disaggregated memory systems

Contention-aware application performance prediction for disaggregated memory systems

Prospects and challenges of virtual machine migration in HPC

Performance Improvements by Deploying L2 Prefetchers with Helper Thread for Pointer-Chasing Applications

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