Addressing instruction fetch bottlenecks by using an instruction register file

Abstract

The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by packing an application's instructions, resulting in decreased code size, reduced energy consumption and improved execution time primarily due to a smaller footprint in the instruction cache. The nature of the IRF also allows the execution of packed instructions to overlap with instruction fetch, thus providing a means for tolerating increased fetch latencies, like those experienced by encrypted ICs as well as the presence of low-power L0 caches. Although previous research has focused on the direct benefits of instruction packing, this paper explores the use of increased fetch bandwidth provided by packed instructions. Small L0 caches improve energy efficiency but can increase execution time due to frequent cache misses. We show that this penalty can be significantly reduced by overlapping the execution of packed instructions with miss stalls. The IRF can also be used to supply additional instructions to a more aggressive execution engine, effectively reducing dependence on instruction cache bandwidth. This can improve energy efficiency, in addition to providing additional flexibility for evaluating various design tradeoffs in a pipeline with asymmetric instruction bandwidth. Thus, we show that the IRF is a complementary technique, operating as a buffer tolerating fetch bottlenecks, as well as providing additional fetch bandwidth for an aggressive pipeline backend.

Enhancing the effectiveness of utilizing an instruction register file

“…These enhancements include improving instruction promotion to the IRF,c hanging instruction selection and performing register re-assignment to increase instruction redundancy, and scheduling of instructions to address packing constraints [4]. We also have shown that an IRF can be used to reduce the execution penalty of an L0/filter IC while further reducing energy consumption [5].…”

“…We hav e also discovered that an IRF can interact effectively with other instruction fetch energy saving architectural features. Forinstance, we studied howan IRF interacts with an L0/filter IC [5]. Figure 8 shows pipeline diagrams for twoe quivalent instruction streams.…”

Fine-grain dynamic instruction placement for L0 scratch-pad memory

“…Copyright 2010 ACM 978-1-60558-903-9/10/10 ...$10.00. 19,20,21,22,7]; in this paper, we call these L0 instruction stores.…”