Addressing reliability challenges in advance nodes for commercial and automotive application

Nigam, T.; Paliwoda, P.; Wang, X.; Kerber, A.

doi:10.1109/iedm19573.2019.8993607

Cited by 7 publications

(5 citation statements)

References 3 publications

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“…However, crystal quality optimization for Si-based III-V materials is still very challenging to achieve good device performance. demonstrated as excellent candidates for high-speed and low-power circuits; these have been proposed for use in sub-10 nm CMOS technology [327,328]. Meanwhile, there is a large challenge to grow high-quality III-V layers on Si substrate for III-V GAAFETs, which stems from the incompatibility of III-V with the Si-based process [329,330].…”

Section: Iii-v Materialsmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Section: Iii-v Materialsmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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“…With CMOS technology development, the reliability issues of advanced CMOS technology are becoming more challenging and complicated due to the novel material, novel process and novel device structure, e.g., Ge/GeSi channels, atom layer etching (ALE) technology, nanowires and nanosheets, etc., specially for 5 nm node and beyond [ 287 , 288 , 289 , 290 ]. Next, the transistor reliability challenge of advanced CMOS will be discussed.…”

Section: Advanced Devices Reliablitymentioning

confidence: 99%

“…Recently, novel devices such as FinFETs, nanowires, and nanosheets, as the best candidates for advanced CMOS technology, have been widely studied [ 287 , 288 ]. In order to meet the better performance of novel devices, advanced processes e.g., filling and etching in 3D device structure, are proposed [ 291 , 292 ].…”

Section: Advanced Devices Reliablitymentioning

confidence: 99%

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State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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“…Nevertheless, despite the efforts to increase orthogonality between HCD and BTI degradation by means of regular ring oscillator (RO)-based monitors, such as conventional inverter chains, where BTI aging predominates over HCD, further refinement of the degradation monitor design is necessary. This refinement aims to increase wear-out due to HCD and achieve significantly orthogonal degradation kinetics across different monitors [ 34 , 35 , 36 , 37 , 38 , 39 ].…”

Section: Introductionmentioning

confidence: 99%

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

Diaz-Fortuny,

Saraza-Canflanca,

Bury

et al. 2024

Micromachines

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The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC.

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Addressing reliability challenges in advance nodes for commercial and automotive application

Cited by 7 publications

References 3 publications

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

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