Addressing the challenges of DBT for the ARM architecture

Moore, Ryan W.; Baiocchi, José A.; Childers, Bruce R.; Davidson, Jack W.; Hiser, Jason D.

doi:10.1145/1542452.1542472

Cited by 24 publications

(8 citation statements)

References 18 publications

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“…In this configuration, the LLVM static compiler used local register allocation and a fast instruction selection algorithm to speed up code generation. This behavior is somewhat similar to other retargetable DBT systems, such as Strata [Scott et al 2003], which use a basic block as a translation unit and have to load/store the architectural state at the translation block boundaries.…”

Section: Llvm Optimization Analysismentioning

confidence: 55%

“…UQDBT [Ung and Cifuentes 2000] and Walkabout [Cifuentes et al 2002a] also support retargetability through the use of specifications of the syntax and semantics of target machine instructions. Strata [Scott et al 2003] is another retargetable BT that defines a reconfigurable target interface. In Strata, only the target-specific functions required by the target interface need to be implemented when retargeting to a new platform.…”

Section: Dynamic Binary Translatorsmentioning

confidence: 99%

“…In addition to the execution time overhead, DBT systems also cause increased memory utilization due to the code cache and the DBT system's own code and data memory. Although this increased memory utilization is small relative to available memory for general-purpose computing environments, it may be extravagant and unacceptable for embedded systems where the memory footprint is a serious concern [Guha et al 2007;Scott et al 2001].…”

Section: Introductionmentioning

confidence: 99%

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A Retargetable Static Binary Translator for the ARM Architecture

Shen

Hsu

Yang

2014

ACM Trans. Archit. Code Optim.

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Machines designed with new but incompatible Instruction Set Architecture (ISA) may lack proper applications. Binary translation can address this incompatibility by migrating applications from one legacy ISA to a new one, although binary translation has problems such as code discovery for variable-length ISA and code location issues for handling indirect branches. Dynamic Binary Translation (DBT) has been widely adopted for migrating applications since it avoids those problems. Static Binary Translation (SBT) is a less general solution and has not been actively researched. However, SBT performs more aggressive optimizations, which could yield more compact code and better code quality. Applications translated by SBT can consume less memory, processor cycles, and power than DBT and can be started more quickly. These advantages are even more critical for embedded systems than for general systems. In this article, we designed and implemented a new SBT tool, called LLBT, which translates ARM instructions into LLVM IRs and then retargets the LLVM IRs to various ISAs, including ×86, ×86-64, ARM, and MIPS. LLBT leverages two important functionalities from LLVM: comprehensive optimizations and retargetability. More importantly, LLBT solves the code discovery problem for ARM/Thumb binaries without resorting to interpretation. LLBT also effectively reduced the size of the address mapping table, making SBT a viable solution for embedded systems. Our experiments based on the EEMBC benchmark suite show that the LLBT-generated code can run more than 6× and 2.3× faster on average than emulation with QEMU and HQEMU, respectively.

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Section: Llvm Optimization Analysismentioning

confidence: 55%

Section: Dynamic Binary Translatorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Retargetable Static Binary Translator for the ARM Architecture

Shen

Hsu

Yang

2014

ACM Trans. Archit. Code Optim.

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“…For example, an ARM program can be executed on an x86 platform with the help of a binary translator. The important technique is widely used in instruction-set-architecture migration [2][3][4][5][6], binary instrumentation [7][8][9], dynamic optimizations [10][11][12][13], software security [14], and fast architecture simulation [15][16][17][18][19]. The Neon and VFP coprocessors [20] are extensions to the ARM architecture.…”

Section: Introductionmentioning

confidence: 99%

Translating the ARM Neon and VFP instructions in a binary translator

et al. 2016

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SUMMARYBinary translation attempts to emulate one instruction set with another on the same or different platforms. The important technique is widely used in modern software. Vector and floating-point instructions are widely used in many applications, including multimedia, graphics, and gaming. Although these instructions are usually simulated with software in a binary translator, it is important to support them such that the host single-instruction, multiple-data (SIMD) and floating-point hardware are efficiently used during emulation. We report our design and implementation of the emulation of ARM Neon and vector floating point (VFP) instructions in the machine-code-to-low-level-virtual-machine (MC2LLVM) binary translator. The Neon and VFP instructions are first translated into carefully chosen sequences of LLVM intermediate representation (IR), and later, the IR sequences are optimized and translated into the host native binary by the existing LLVM backend. Because MC2LLVM makes use of the vector and floating-point types in LLVM IR, the generated host native binary can take full advantage of the vector and floating-point functional units, if present, of the host machine. To be fully compliant with Neon and VFP instruction sets, all the features are supported, including the flush-to-zero mode, default not a number mode, and floating-point exceptions. The experimental results show that code generated by MC2LLVM with the Neon and VFP extensions achieves an average speedup of 1.174 in SPEC 2006 benchmark suites and exhibits a floating-point throughput of 12.05 in LINPACK, compared with code generated by MC2LLVM without the Neon and VFP extensions. Furthermore, MC2LLVM is 3.36 faster than QEMU for processing Neon/VFP instructions.

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“…This additional code storage obviously introduces memory footprint overheads. Some VMs propose new memory management algorithms [24], [25]. The main problem between all these optimizations is related to the strong impact on application execution, using its dedicated resources.…”

Section: B Performance and Energy Consumption Overheads Introduced By mentioning

confidence: 99%

Hardware acceleration for Just-In-Time compilation on heterogeneous embedded systems

Carbon¹,

Lhuillier²,

Charles³

2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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Embedded systems are increasingly complex and heterogeneous to deal with increasing performance requirements along with wider ranges of application domains. The architecture of such systems often includes different kinds of computing resources and accelerators (DSPs, GPUs, etc.). Thus, application developers are facing important portability issues to adapt their software code to take maximum advantage of available processing elements. Consequently, software stacks rely more and more on virtualization technologies, leveraging Just-In-Time compilation to maximize performance of applications. Nevertheless, the efficiency of Just-In-Time compilation depends on the ability to compensate its overhead with execution speedups of generated code. In this paper, we propose a solution based on a dedicated processor with specialized instructions for critical functions to improve efficiency of code generators. These specialized instructions provide an average 5× speedup on manipulations of associative arrays and dynamic memory allocation. Based on the LLVM framework, we show a 15% overall speedup on code generator's execution time. Because our specialized instructions are hidden behind standard libraries, we also argue that these instructions may be transparently reused for a wider range of applications.978-1-4799-0493-8/13/$31.00

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Addressing the challenges of DBT for the ARM architecture

Cited by 24 publications

References 18 publications

A Retargetable Static Binary Translator for the ARM Architecture

A Retargetable Static Binary Translator for the ARM Architecture

Translating the ARM Neon and VFP instructions in a binary translator

Hardware acceleration for Just-In-Time compilation on heterogeneous embedded systems

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