Admittance of Barrier Structures Based on Mercury Cadmium Telluride

Studying C-V characteristics of MIS structures with ALD Al-=SUB=-2-=/SUB=-O-=SUB=-3-=/SUB=- on n- and p-CdHgTe stabilized with ultra-thin native oxide

“…1 that structures with a surface graded-gap layer differ fundamentally from those without it both in the nature of variation of the surface potential and the electric capacitance of a semiconductor in transition from depletion to inversion (the capacitance minimum is broader) and in that a well-marked CVC hysteresis loop forms under cyclic gate voltage sweep. The authors of [28] have proposed an explanation for weaker hysteresis in structures based on MCT without an SGGL. They point out that the surface potential of a semiconductor with a wide-gap layer varies within a wider range under gate voltage sweep than the surface potential of a narrow-gap semiconductor, and this results in trapping of a greater number of carriers at slow surface states and is manifested in a wider CVC hysteresis.…”

“…In the case of structures with a graded-gap layer, the experimental data also deviate from the theoretical ones in the region of depletion−weak inversion. The authors of [28] have noted that if a graded-gap layer is present on the Cd 0.22 Hg 0.78 Te surface, the recharge time of surface states is so long that the capacitance-voltage characteristic is high-frequency relative to it (even if this characteristic is low-frequency relative to the lifetime of minority carriers). This implies that the observed deviation cannot be associated unambiguously with the contribution of capacitance of fast surface states to the resulting MIS capacitance.…”