Advanced BEOL Interconnects

Nogami, Takeshi; Gaidai, Oleg; Sulehria, Yasir; Nguyen, S.; Huang, Huai; Lanzillo, Nicholas A.; DeSilva, Anuja; Mignot, Yann; Church, Jennifer; Lee, Joe; Bhosale, Prasad; Patlolla, R.; Sil, Devika; Shobha, H.; Kelly, James; Li, Juntao; Demarest, J.; Simon, A.; Clevenger, L. A.; Edelstein, Brown Peethala Dan; Haran, Bala

doi:10.1109/iitc47697.2020.9515628

Cited by 7 publications

(3 citation statements)

References 2 publications

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“…The EM performance of Ru-Cu hybrid metalization is similar to the full copper metalization. A selective tungsten (W) deposition has also been used for via pre-filling [313]. Compared with the Cu dual damascene-filled via layer, the via resistance of W-Cu hybrid metalization is reduced by 40%.…”

Section: Metal Materials Interconnectmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Section: Metal Materials Interconnectmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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“…As it limits the growth of metallic grains and results in the increasing density of grain boundaries, electron scattering starts to bring a serious demerit in line resistivity. In fact, there is an exponential relationship between the increase of the line resistivity and the scaling of the cross-sectional area of the BEOL lines (Figure 12) [61][62][63][64]. Beyond the 7 nm technology node, alternative metals such as Ru [61,63,65] and cobalt (Co) [61,66,67] start to be considered because of their potential benefit in line resistivity.…”

Section: Beol Applicationsmentioning

confidence: 99%

“…In fact, there is an exponential relationship between the increase of the line resistivity and the scaling of the cross-sectional area of the BEOL lines (Figure 12) [61][62][63][64]. Beyond the 7 nm technology node, alternative metals such as Ru [61,63,65] and cobalt (Co) [61,66,67] start to be considered because of their potential benefit in line resistivity. The figure of merit is determined by a complex combination among bulk resistivity, the cross-sectional area of lines, the mean-free-path of electrons, electro-migration reliability (i.e., melting point of metals), integration compatibility (e.g., availability of raw materials, process uniformity), and the impacts from a barrier and liner.…”

Section: Beol Applicationsmentioning

confidence: 99%

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

et al. 2022

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The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices.

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Atomistic insights into adhesion characteristics of tungsten on titanium nitride using steered molecular dynamics with machine learning interatomic potential

Cho,

Son,

Cho

et al. 2023

Sci Rep

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As transistor integration accelerates and miniaturization progresses, improving the interfacial adhesion characteristics of complex metal interconnect has become a major issue in ensuring semiconductor device reliability. Therefore, it is becoming increasingly important to interpret the adhesive properties of metal interconnects at the atomic level, predict their adhesive strength and failure mode, and develop computational methods that can be universally applied regardless of interface properties. In this study, we propose a method for theoretically understanding adhesion characteristics through steering molecular dynamics simulations based on machine learning interatomic potentials. We utilized this method to investigate the adhesion characteristics of tungsten deposited on titanium nitride barrier metal (W/TiN) as a representative metal interconnect structure in devices. Pulling tests that pull two materials apart and sliding tests that pull them against each other in a shear direction were implemented to investigate the failure mode and adhesive strength depending on TiN facet orientation. We found that the W/TiN interface showed an adhesive failure where they separate from each other when tested with pulling force on Ti-rich (111) or (001) facets while cohesive failures occurred where W itself was destroyed on N-rich (111) facet. The adhesion strength was defined as the maximum force causing failure during the pulling test for consistent interpretation and the strengths of tungsten were predicted to be strongest when deposited onto N-rich (111) facet while weakest on Ti-rich (111) facet.

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Advanced BEOL Interconnects

Cited by 7 publications

References 2 publications

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices

Atomistic insights into adhesion characteristics of tungsten on titanium nitride using steered molecular dynamics with machine learning interatomic potential

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