Advanced Concepts for Floating-Body Memories

Abstract

With 30nm-class memory cells in production and 20nm-class (20-29nm feature-size) memory targeted for next year, the standard 1-Transistor + 1-Capacitor (1T+1C) DRAM industry is making prominent efforts to improve the scalability of the cell capacitor while maintaining the minimum capacitance requirements for state discrimination, immune to noise (C~25fF/cell). To achieve the capacitance requirement, the DRAM cell has evolved from its initial planar implementation to complex three-dimensional structures. The increment in complexity and the large difference in size between the transistor and capacitor of each cell have motivated the search for Floating-Body Single-Transistor DRAM (1T-DRAM). The underlying idea behind 1T-DRAMs is the development of single-device memory cells with a pronounced hysteresis effect and fast operation. This chapter is focused on the floating-body effect as a primary source of hysteresis. We present new concepts able to deal with the basic limitations of 1T-DRAM while maintaining its simplicity. The floating-body 1T-DRAMs can be reconciled with the aggressive scaling constrains by considering new ideas which make possible the coexistence of electron and holes in the same ultrathin transistor. The best approach is to isolate each type of carrier in an specific potential well which is not created specifically by the bias conditions (unlike standard 1T-DRAMs) but by the physical structure of the device.